<13/54>VDP1 User's Manual/4.2 Frame Buffer Switching Mode Register

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VDP1 User's Manual/Chapter 4 System Registers

■4.2 Frame buffer switching mode register

The Frame Buffer Change Mode Register (FBCR) controls switching between drawing and displaying the frame buffer and drawing double-dense interlacing. This is a 16-bit write-only register located at address 100002H. After the power is turned on or reset, the value becomes undefined, so be sure to set the switching mode. Set unused bits to 0.

FBCR 100002H (W) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 0 0 0 0 0 0 EOS DIE DIL FCM FCT

Frame buffer change mode bit: frame buffer change mode (FCM), bit1

Frame buffer change trigger bit: frame buffer change trigger (FCT), bit0

Typically, two frame buffers are used, one as the front and the other as the back. Leave the front side visible and draw on the back side. Then, after one frame switching time has passed, the front and back sides are toggled. The front side that was displayed becomes the back side that is drawn, and the back side that was drawn becomes the front side that is displayed. Frame buffer access can only be made on the drawing side. This is not possible on the display side. There is a limit to the number of characters that can be drawn in one frame, so if you want to draw many characters, set it to manual mode and control erase and change from the CPU. When any data is written from the CPU to FBCR, the values of FCM and FCT are updated inside VDP1 when the field changes. In manual mode, the FCT bit setting is valid only for the next frame. When a frame changes, the contents of FCT are updated internally. Set FCM and FCT immediately after the V blank OUT interrupt. Access is prohibited from the first H blank IN interrupt after the V blank OUT interrupt until the next H blank IN interrupt.

FBCR 100002H (W)	bit15	bit14	bit13	bit12	bit11	bit10	bit9	bit8	bit7	bit6	bit5	bit4	bit3	bit2	bit1	bit0
0	0	0	0	0	0	0	0	0	0	0	EOS	DIE	DIL	FCM	FCT

VBE	FCM	FCT	switching mode	switching time
0	0	0	1 cycle mode	Changes every 1/60 seconds
0	0	1	Setting prohibited	−
0	1	0	Manual mode (erase)	Erase in next field
0	1	1	Manual mode (change)	Change in next field
1	0	0	Setting prohibited	−
1	0	1	Setting prohibited	−
1	1	0	Setting prohibited	−
1	1	1	manual mode (Erase & Change)	Erase with V blank, Change in next field

1 cycle mode

This is normal mode. One frame changes automatically every 1/60 seconds. Set the VBE and FCT bit values to 0.

Erase (manual mode)

Control one frame erase write from CPU. Specify manual erase write of the frame buffer by writing to the registers with VBE=0, FCM=1, and FCT=0. Erase writes to the display frame buffer on the next specified field, clearing the display frame buffer. There is no switching between drawing and display framebuffers. When you erase, the display frame buffer is cleared, so if you want to display it, you must specify change in the field after specifying erase to switch between drawing and display. Use this mode when one frame consists of two or more fields, such as double-dense interlacing. Also, when switching from manual mode to 1 cycle mode, use this erase in the field before switching. Erase is used when you know that a frame change will occur in the next field. If the frame change is unknown up to the previous field, use Erase & Change.

Change (manual mode)

The switching of one frame is controlled from the CPU. Specify switching by writing to the registers with VBE=0, FCM=1, and FCT=1. The next specified field will be toggled between drawing and display. Since no erase write is performed, it is necessary to specify erase in the field immediately before specifying change and erase write the frame buffer. You can draw characters on the back side until you instruct to switch. Normally, this change is used when switching from 1 cycle mode to manual mode. Also, use this change when switching frame buffers in manual mode.

Erase & Change (Manual mode)

Setting VBE = 1 in the register specifies V blank erase, and setting FCM = 1 and FCT = 1 specifies frame buffer switching after V blank. Use this when the frame change is unknown up to the previous V blank, such as when not switching frame buffers until CPU processing is finished. Once VBE is set to 1, erase writing will be performed automatically on the next V blank, so after a frame change, set VBE to 0 before the next V blank. Perform erase and change settings immediately after the V blank IN interrupt. If you set it to anything else, it may change without being able to be erased. If you are using normal or high resolution, and you know the frame change timing in advance, such as with interlace, specify erase and change and perform an erase write during the display period. In this case, it is possible to erase/write the entire display screen.

●Sequence when using erase & change

Set VBE=0, FCM=1, FCT=1. Wait for the CPU, etc. to finish processing without setting TV mode selection or FB switching mode. If CPU processing is completed by the H blank IN interrupt immediately before the V blank (224th line when 224 lines are displayed, 240th line when 240 lines are displayed), VBE = 1, FCM = 1, FCT = 1 ( Erase & Change). Perform erase and change settings immediately after the V blank IN interrupt. After the V blank IN interrupt ends, the V blank erase starts. At the end of the V blank, the erase write is interrupted and a frame change is performed. If the erase write is not completed, please erase the unerased area using polygons. Immediately after the V blank OUT interrupt, return VBE to 0 to stop V blank erase. Return to (2).

●Usage example

Here is an example using framebuffer switching mode.

Table 4.3(a) Example of using frame buffer switching mode (VBE=0 fixed)

Setting value *1		*2 frame buffer 0	*2 frame buffer 1	frame buffer switching mode	switching time
FCM	FCT	*2 frame buffer 0	*2 frame buffer 1	frame buffer switching mode	switching time
0	0	drawing	Display + erase write	1 cycle mode	60 frames/sec
		Display + erase write	drawing
		drawing	Display + erase write
		Display + erase write	drawing
1	1	drawing	Display + erase write	Manual mode (change)*3
		display	drawing		20 frames/sec
1	0	display	drawing	Manual mode (erase)*4
1	1	Display + erase write	drawing	Manual mode (change) *4
		drawing	display
1	0	drawing	display	Manual mode (erase)*5
0	0	drawing	Display + erase write	1 cycle mode
		Display + erase write	drawing		60 frames/sec
		drawing	Display + erase write		60 frames/sec

[note]

*1 This is the value written to the register immediately after the V blank OUT interrupt.

*2 Switches from the beginning of the field

*3 changes switches from 1 cycle mode to manual mode

*4Erase and change must be specified consecutively.

*5 Please specify erase in the field immediately before switching to 1 cycle mode.

Table 4.3(b) Example of using frame buffer switching mode (using VBE)

Double interlace enable bit: double interlace enable (DIE), bit3

Double interlace plot line: double interlace plot line(DIL), bit2

Simple dense interlacing displays the same picture in even and odd fields. On the other hand, double-dense interlacing doubles the vertical resolution by displaying different pictures (drawing only even and odd lines, respectively) in even and odd fields. DIE=1 enables double-dense interlacing. The contents of the first display screen after changing DIE are not guaranteed. For double-dense interlacing, set FCM=FCT=0 (1 cycle mode) to switch fields every 1/60 seconds.

D.I.E.	DIL	interlaced mode	Drawing after next frame change
0	0	Non-interlaced/ Single dense interlace	Full line drawing
0	1	Setting prohibited	−
1	0	double dense interlace	Draw only even numbered (EVEN) lines
1	1	double dense interlace	Draw only odd number (ODD) lines

Figure 4.1 Displaying single-dense and double-dense interlacing

●Single-dense interlace display                ●Double-dense interlace display　
┌────────┐                                     ┌────────┐　
│ 0 line ├────────┐                            │ 0 line ├────────┐
├────────┤ 0 line │                            ├────────┤ 1 line │
│ 1 line ├────────┤                            │ 2 lines├────────┤
├────────┤ 1 line │                            ├────────┤ 3 lines│
│ 2 lines├────────┤                            │ 4 lines├────────┤
├────────┤ 2 lines│                            ├────────┤ 5 lines│
│ 3 lines├────────┤                            │ 6 lines├────────┤
└────────┤ 3 lines│                            └────────┤ 7 lines│
         └────────┘                                     └────────┘
・Appears to be 256 vertical lines              ・Appears to be 512 vertical lines　
・Frame changes every 1/60 seconds              ・Only even (or odd) lines are drawn in each frame buffer.
・Either change the frame every 1/60 seconds
 and draw the same thing twice, or change
 the frame every 1/30 seconds
 (instructed by the CPU using a 1/60 second
 signal)

Even/odd coordinate select bit: even/odd coordinate select bit(EOS), bit4

This bit is enabled when High Speed Shrink (HSS) is set to 1 for a rectangular sprite or a deformed sprite. If HSS=1 is specified, lines where the drawing magnification is <1 will be drawn by sampling only pixels at either even or odd coordinates of the original picture data. This bit specifies whether even or odd coordinates are to be sampled.

When EOS=0, only pixels with even coordinates are sampled. When EOS=1, only pixels at odd coordinates are sampled.

If HSS=0 is specified, this bit is not referenced.

For more information, please refer to " High Speed Shrink " in " 6.3 Drawing Mode Words ".

EOS	Even/odd coordinate selection bit
0	Sample only pixels with even coordinates
1	Sample only pixels with odd coordinates

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