Japanese
★ HARDWARE Manual ★ VDP2 User's Manual ★ Chapter 2 TV Screen
▲ Back ｜ Forward ▼
VDP2 User's Manual/Chapter 2 TV Screen

■2.5 External signals and scanning status

The registers that control external signals include the external signal enable register, and the registers that display the TV scanning status include the screen status register, H counter register, and V counter register.

●External signal enable register

The external signal enable register controls signals from outside the VDP2. This is a 16-bit readable and writable register located at address 180002H. The value is cleared to 0 after power-on or reset, so be sure to set it.

EXTEN 180002H
   15   
   14   
   13   
   12   
   11   
   10   
   09   
   08
- - - - - - EXLTEN EXSYEN

   07   
   06   
   05   
   04   
   03   
   02   
   01   
   00
- - - - - - DASEL EXBGEN

▲ External latch enable bit : External latch enable bit (EXLTEN), bit 9
Specify the conditions for latching the HV counter value into the HV counter register.

 EXLTEN
 condition
 0
 Latch when external signal enable register is read
 1
 Latch by external signal

The latched H counter value can be read in the H counter register, and the V counter value can be read in the V counter register.
Set this to 1 when reading the H and V counter values using an external signal such as a ray gun . Normally set to 0.

▲ External synchronization enable bit : EXSYNC enable bit (EXSYEN), bit 8
Controls input of external synchronization signal to internal synchronization circuit.

 EXSYEN
 process
 0
 Do not input external synchronization signal
 1
 Inputting an external synchronization signal to synchronize the TV screen display with the external device

If you want to synchronize the screen display with another device, set it to 1 and input an external synchronization signal. Normally, leave it at 0.

▲ Image display area select bit : Display area select bit (DASEL), bit 1
Specify the image display area. Valid only when the EXBGEN bit is 1.

 DASEL
 process
 0
 Display images only in the settings display area
 1
 Display images in all standard display areas

When displaying in all standard display areas, images based on external screen data will be displayed correctly in all areas. However, images outside of the settings display area (sprites, scroll screens, etc.) cannot be displayed correctly. Therefore, use a window to force other images to be transparent except for the settings display area.

▲ External screen enable bit : EXBG enable bit (EXBGEN), bit 0
Controls input of external screen data.

 EXBGEN
 process
 0
 Do not enter external screen data
 1
 Enter external screen data

When inputting external screen data, that data becomes NBG1 screen data, so the external screen settings for NBG1 are used.
Table 2.2 shows the register bits for external screen settings.

Table 2.2 Registers for external screen settings
 address
 bit number
 Bit name
 180020H
 9
 N1TPON
 Transparent display enable
 180028H
 13, 12
 N1CHCN1, N1CHCN0
 Number of character colors
 1800D0H
 8
 N1W0A
 W0 window area
 9
 N1W0E
 W0 window enable
 10
 N1W1A
 W1 window area
 11
 N1W1E
 W1 window enable
 12
 N1SWA
 SW window area
 13
 N1SWE
 SW window enable
 15
 N1LOG
 window logic
 1800E2H
 1
 N1SDEN
 shadow enable
 1800E4H
 6 to 4
 N1CAOS2～N1CAOS0
 Color RAM address offset
 1800E8H
 1
 N1LCEN
 Line color screen insertion enable
 1800EAH
 3, 2
 N1SPRM1, N1SPRM0
 Special priority mode
 1800ECH
 1
 N1CCEN
 Color calculation enable
 1800EEH
 3, 2
 N1SCCM，N1SCCM0
 Special color calculation mode
 1800F8H
 10~8
 N1PRIN2～N1PRIN0
 priority number
 180118H
 12-8
 N1CCRT4～N1CCRT0
 Color calculation ratio
 180110H
 1
 N1COEN
 color offset enable
 180112H
 1
 N1COSL
 color offset selection

●Screen status register

The screen status register displays information on the TV screen. This is a 16-bit read-only register located at address 180004H.

TVSTAT 180004H
   15   
   14   
   13   
   12   
   11   
   10   
   09   
   08
- - - - - - EXLTFG EXSYFG

   07   
   06   
   05   
   04   
   03   
   02   
   01   
   00
- - - - VBLANK HBLANK O.D.D. PAL

▲ External latch flag : External latch flag (EXLTFG), bit 9
Indicates whether the HV counter value is latched into the HV counter register by an external signal. It is cleared to 0 when the screen status register is read.

 EXLTFG
 HV counter value status
 0
 Not yet latched into a register
 1
 latched in register

▲ External SYNC flag (EXSYFG), bit 8
Indicates whether the internal circuit has been synchronized by an external synchronization signal. It is cleared to 0 when the screen status register is read.

 EXSYFG
 External synchronization status
 0
 not synced
 1
 Internal circuits are synchronized

▲ V blank flag : Vertical blank flag (VBLANK), bit 3
Indicates the vertical scanning status of the TV screen.

 VBLANK
 Vertical scanning state
 0
 Scanning is during vertical display period
 1
 Scanning is during vertical retrace period (during VBLANK period)

This bit is valid only when the TV screen display bit ( DISP ) in the TV screen mode register is 1. When the TV screen display bit ( DISP ) is 0, the V blank flag ( VBLANK ) is always 1.

▲ H blank flag : Horizontal blank flag (HBLANK), bit 2
Indicates the horizontal scanning status of the TV screen.

 HBLANK
 Horizontal scanning state
 0
 Scanning is during horizontal display period
 1
 Scanning is during horizontal retrace period (during HBLANK period)

▲ Scanning field flag : Odd/even field flag (ODD), bit 1
Indicates the scanning status when the TV screen mode is interlaced mode.
In non-interlaced mode, it is always 1.

 O.D.D.
 display
 0
 Scan during even field period
 1
 Scanning during odd field period

▲ TV system flag : PAL/NTSC flag (PAL), bit 0
Indicates the TV system status.

 PAL
 display
 0
 NTSC method
 1
 PAL method

●H counter register

The H counter register indicates the H counter value. This is a read-only 16-bit register located at address 180008H.

HCNT 180008H
   15   
   14   
   13   
   12   
   11   
   10   
   09   
   08
- - - - - - HCT9 HCT8

   07   
   06   
   05   
   04   
   03   
   02   
   01   
   00
HCT7 HCT6 HCT5 HCT4 HCT3 HCT2 HCT1 HCT0

▲ H counter value bit : H counter bit (HCT9 to HCT0), bits 9 to 0
This signal is controlled by the external signal enable register EXLTEN and represents the value of the latched H counter. The bit configuration of this register changes depending on the graphics mode setting, as shown in Table 2.3.
In the case of normal graphics, the H counter value has the least significant bit HCT0 as invalid data. In the case of dedicated normal graphics, the H counter value has the most significant bit HCT9 as invalid data.
Also, in the case of dedicated high resolution graphics, the H counter value will be a value in units of 2 dots because the most significant bit HCT9 is invalid data and there is no bit for H0.

Table 2.3 H counter register bit contents
 graphic
 mode
 HCT9
 HCT8
 HCT7
 HCT6
 HCT5
 HCT4
 HCT3
 HCT2
 HCT1
 HCT0
 normal
 H8
 H7
 H6
 H5
 H4
 H3
 H2
 H1
 H0
 invalid
 high resolution
 H9
 H8
 H7
 H6
 H5
 H4
 H3
 H2
 H1
 H0
 exclusive
 normal
 invalid
 H8
 H7
 H6
 H5
 H4
 H3
 H2
 H1
 H0
 exclusive
 high resolution
 invalid
 H9
 H8
 H7
 H6
 H5
 H4
 H3
 H2
 H1

●V counter register

The V counter register indicates the V counter value. This is a 16-bit read-only register located at address 18000AH.

VCNT 18000AH
   15   
   14   
   13   
   12   
   11   
   10   
   09   
   08
- - - - - - VCT9 VCT8

   07   
   06   
   05   
   04   
   03   
   02   
   01   
   00
VCT7 VCT6 VCT5 VCT4 VCT3 VCT2 VCT1 VCT0

▲ V counter value bit : V counter bit (VCT9 to VCT0), bits 9 to 0
This signal is controlled by the external signal enable register EXLTEN and represents the value of the latched V counter. The bit configuration of this register changes depending on the TV screen mode setting, as shown in Table 2.4. The V counter value in the case of single dense interlacing in normal and high resolution modes represents the V counter value in each of the even and odd fields. In the case of double-density interlacing in normal and high resolution modes, the V counter value indicates an odd field when the least significant bit VCT0 is 0, an even field when it is 1, and VCT1 to VCT9 are the values in each field. Represents the V counter value.

Table 2.4 V counter register bit contents
 TV screen mode
 (interlaced)
 VCT9
 VCT8
 VCT7
 VCT6
 VCT5
 VCT4
 VCT3
 VCT2
 VCT1
 VCT0
 normal,
 high resolution
 (Non-interlaced,
 single dense interlace)
 V9
 V8
 V7
 V6
 V5
 V4
 V3
 V2
 V1
 V0
 normal,
 high resolution,
 (Double dense interlace)
 V8
 V7
 V6
 V5
 V4
 V3
 V2
 V1
 V0
 0: odd number
 1: Even number
 exclusive
 monitor
 V9
 V8
 V7
 V6
 V5
 V4
 V3
 V2
 V1
 V0

▲ Back ｜ Forward ▼
★ HARDWARE Manual ★ VDP2 User's Manual ★ Chapter 2 TV Screen
Copyright SEGA ENTERPRISES, LTD., 1997