<38/86>VDP2 User's Manual/5.3 Line & Vertical Cell Scroll Function

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VDP2 User's Manual/Chapter 5 Normal scroll screen

■5.3 Line & vertical cell scrolling function

In the normal scroll screen, NBG0 and NBG1 have line scroll function and vertical cell scroll function. The line scroll function specifies the horizontal and vertical screen scroll values and horizontal coordinate increments in line units. The vertical cell scroll function specifies the vertical screen scroll value for each horizontal cell. Both functions can be used regardless of cell format or bitmap format.

●Line scroll function

The line scroll function is a function that allows you to specify the horizontal and vertical screen scroll values and horizontal coordinate increments in line units, using a line scroll table stored in VRAM. Data values in the line scroll table are specified using relative values. The value specified in the screen scroll value register is added to the screen scroll value stored in the line scroll table to form the display coordinates. The interval for reading table data can be selected from four types: 1 line, 2 lines, 4 lines, and 8 lines. If you select an interval of 2 lines or more, the vertical coordinate calculation will be performed using the vertical coordinates. The value in the increment register is used.
Do not set the horizontal coordinate increment to a value that exceeds the reduction enable register setting. The line scroll function is shown in Figure 5.3.

Figure 5.3 Line scroll function

Line scroll table (VRAM)     Horizontal coordinate
                             increment            
                           → → → →   Scroll screen
┏━━━━━━━━━━━━━━━━━━━━┓     ┏━┯━┯━┯━┯━┯━┯━         
┃1st line horizontal ┃┐┌──→┃ │ │ │ │ │ │ 1st line 
┃screen scroll value ┃││   ┃ │ │ │ │ │ │          
┠────────────────────┨││   ┣━┿━┿━┿━┿━┿━┿━         
┃1st line vertical   ┃├┘┌─→┃ │ │ │ │ │ │ 2nd line 
┃screen scroll value ┃│ │  ┃ │ │ │ │ │ │          
┠────────────────────┨│ │  ┣━┿━┿━┿━┿━┿━┿━         
┃1st line horizontal ┃┘ │  ┃ │ │ │ │ │ │ 3rd line 
┃coordinate increment┃  │  ┃ │ │ │ │ │ │          
┣━━━━━━━━━━━━━━━━━━━━┫  │  ┣━┿━┿━┿━┿━┿━┿━         
┃2nd line horizontal ┃┐ │  ┃ │ │ │ │ │ │ 4th line 
┃screen scroll value ┃│ │  ┃ │ │ │ │ │ │          
┠────────────────────┨│ │  ┣━┿━┿━┿━┿━┿━┿━         
┃2nd line vertical   ┃├─┘  ┃ │ │ │ │ │ │ 5th line 
┃screen scroll value ┃│    ┃ │ │ │ │ │ │          
┠────────────────────┨│    ┣━┿━┿━┿━┿━┿━┿━         
┃2nd line horizontal ┃┘    ┃ │ │ │ │ │ │          
┃coordinate increment┃     ┃ │ │ │ │ │ │          
┣━━━━━━━━━━━━━━━━━━━━┫

The line scroll table stores the horizontal screen scroll value, vertical screen scroll value, and horizontal coordinate increment in the order starting from the smallest address. The line scroll data to be stored consists only of the data required according to the settings of the line scroll register.
The configuration of each horizontal screen scroll value, vertical screen scroll value, and horizontal coordinate increment on the line scroll table is the same as the configuration of the data set in each register. Figure 5.4 shows the bit configuration of line scroll table data, and Figure 5.5 shows the line scroll table configuration.

Figure 5.4 Bit configuration of line scroll table data

●Horizontal and vertical screen scroll value registers　
Bit F E D C B A 9 8 7 6 5 4 3 2 1 0　
   ┌─┬─┬─┬─┬─┰─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┐
+0H│−│−│−│−│−┃Integer part(11 bits)│
   └─┴─┴─┴─┴─┸─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┘
　
Bit F E D C B A 9 8 7 6 5 4 3 2 1 0　
   ┌─┬─┬─┬─┬─┬─┬─┬─┰─┬─┬─┬─┬─┬─┬─┬─┐
+2H│Decimal part   ┃−│−│−│−│−│−│−│−│
   │(8 bits)       ┃ │ │ │ │ │ │ │ │
   └─┴─┴─┴─┴─┴─┴─┴─┸─┴─┴─┴─┴─┴─┴─┴─┘
　
●Horizontal coordinate increment　
Bit F E D C B A 9 8 7 6 5 4 3 2 1 0　
   ┌─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┐
+0H│−│−│−│−│−│−│−│−│−│−│−│−│−│Int  │
   │ │ │ │ │ │ │ │ │ │ │ │ │ │part │
   └─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┘
　
Bit F E D C B A 9 8 7 6 5 4 3 2 1 0　
   ┌─┬─┬─┬─┬─┬─┬─┬─┰─┬─┬─┬─┬─┬─┬─┬─┐
+2H│Decimal part   ┃−│−│−│−│−│−│−│−│
   │(8 bits)       ┃ │ │ │ │ │ │ │ │
   └─┴─┴─┴─┴─┴─┴─┴─┸─┴─┴─┴─┴─┴─┴─┴─┘
　
[Note] "-" is ignored

Figure 5.5 Line scroll table example

●When specifying horizontal and vertical screen scroll values and horizontal coordinate increments for each line　
                         Line scroll table (VRAM)    
                    MSB                           LSB
                   ┌────────────────────────────────┐
Line scroll ─→ +00H│ 1st line horizontal screen     │
table address      │ scroll value (integer part)    │
                   ├────────────────────────────────┤
               +02H│ 1st line horizontal screen     │
                   │ scroll value (decimal part)    │
                   ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
               +04H│ 1st line vertical screen       │
                   │ scroll value (integer part)    │
                   ├────────────────────────────────┤
               +06H│ 1st line vertical screen       │
                   │ scroll value (decimal part)    │
                   ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
               +08H| 1st line horizontal coordinate |
                   | increment (integer part)       |
                   ├────────────────────────────────┤
               +0AH│ 1st line horizontal coordinate │
                   │ increment (decimal part)       │
                   ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
               +0CH│ 2nd line horizontal screen     │
                   │ scroll value (integer part)    │
                   ├────────────────────────────────┤
               +0EH│ 2nd line horizontal screen     │
                   │ scroll value (decimal part)    │
                   ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
               +10H| 2nd line vertical screen       |
                   | scroll value (integer part)    |
                   ├────────────────────────────────┤
               +12H| 2nd line vertical screen       |
                   | scroll value (decimal part)    |
                   ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
               +14H| 2nd line horizontal coordinate |
                   | increment (integer part)       |
                   ├────────────────────────────────┤
               +16H| 2nd line horizontal coordinate |
                   | increment (decimal part)       |
                   ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥

●When specifying the vertical screen scroll value and horizontal coordinate increment every two lines 
                         Line scroll table (VRAM)    
                    MSB                                LSB
                   ┌─────────────────────────────────────┐
Line scroll ─→ +00H│ 1st line vertical screen            │
table address      │ scroll value (integer part)         │
                   ├─────────────────────────────────────┤
               +02H│ 1st line vertical screen            │
                   │ scroll value (decimal part)         │
                   ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
               +04H| 1st and 2nd line horizontal         |
                   | coordinate increment (integer part) |
                   ├─────────────────────────────────────┤
               +06H│ 1st and 2nd line horizontal         │
                   │ coordinate increment (decimal part) │
                   ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
               +08H| 3rd line vertical screen            |
                   | scroll value (integer part)         |
                   ├─────────────────────────────────────┤
               +0AH│ 3rd line vertical screen            │
                   │ scroll value (decimal part)         │
                   ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
               +0CH│ 3rd and 4th line horizontal         │
                   │ coordinate increment (integer part) │
                   ├─────────────────────────────────────┤
               +0EH│ 3rd and 4th line horizontal         │
                   │ coordinate increment (decimal part) │
                   ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
 
[Note] The vertical display coordinates of lines other than the specified line are
the vertical screen scroll value of the specified line plus the vertical coordinate increment.

●When the horizontal screen scroll value and horizontal coordinate increment are specified every 4 lines (no vertical line scroll)
                         Line scroll table (VRAM)    
                    MSB                                LSB
                   ┌─────────────────────────────────────┐
Line scroll ─→ +00H│ Horizontal screen scroll value for  │
table address      │ 1st to 4th lines (integer part)     │
                   ├─────────────────────────────────────┤
               +02H| Horizontal screen scroll value for  |
                   | 1st to 4th lines (decimal part)     |
                   ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
               +04H| Horizontal coordinate increment of  |
                   | 1st to 4th lines (integer part)     |
                   ├─────────────────────────────────────┤
               +06H| Horizontal coordinate increment for |
                   | 1st to 4th lines (decimal part)     |
                   ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
               +08H| Horizontal screen scroll value for  |
                   | 5th to 8th lines (integer part)     |
                   ├─────────────────────────────────────┤
               +0AH| Horizontal screen scroll value for  |
                   | 5th to 8th lines (decimal part)     |
                   ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
               +0CH| Horizontal coordinate increment of  |
                   | 5th to 8th lines (integer part)     |
                   ├─────────────────────────────────────┤
               +0EH| Horizontal coordinate increment of  |
                   | 5th to 8th lines (decimal part)     |
                   ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥

●Vertical cell scrolling function

The vertical cell scroll function is a function that allows you to specify the vertical screen scroll value for each area divided vertically in units of horizontal cells, and is specified using the vertical cell scroll table stored in VRAM. Data values in the vertical cell scroll table are specified using relative values. The value specified in the screen scroll value register is added to the screen scroll value stored in the vertical cell scroll table to form the display coordinates. When displaying in bitmap format, you can specify in units of 8 dots in the horizontal direction.
Among the normal scroll screens, only NBG0 and NBG1 have a vertical cell scrolling function. This vertical cell scrolling function and the mosaic function cannot be used at the same time; the mosaic function takes priority.
The vertical cell scrolling function is shown in Figure 5.6.

Figure 5.6 Vertical cell scrolling function

 Vertical cell scroll table (VRAM)              
┌─────────────────┐                             
│Vertical screen  │──┐                          
│scroll value of  │  │                          
│1st cell         │  │                          
├─────────────────┤  │                          
│Vertical screen  │──┼─┐                        
│scroll value of  │  │ │                        
│2nd cell         │  │ │                        
├─────────────────┤  │ │                        
│Vertical screen  │──┼─┼─┐                      
│scroll value of  │  │ │ │                      
│3rd cell         │  │ │ │                      
├─────────────────┤  │ │ │                      
                  │  │ │ │                      
                     ↓ ↓ ↓                      
                    │ │ │ │ │ │ │ │ │           
                   ─┼─┼─┼─┼─┼─┼─┼─┼─┼─          
                    │┏┿━┿━┿━┿━┿━┿━┿━┿━━TV screen
                   ─┼╂┼─┼─┼─┼─┼─┼─┼─┼─          
                    │┃│ │ │ │ │ │ │ │           
                   ─┼╂┼─┼─┼─┼─┼─┼─┼─┼─          
                    │┃│ │ │ │ │ │ │ │           
                   ─┼╂┼─┼─┼─┼─┼─┼─┼─┼─          
                    │┃│ │ │ │ │ │ │ │           
                   ─┼╂┼─┼─┼─┼─┼─┼─┼─┼─          
                    │┃│ │ │ │ │ │ │ │           
                   ─┼╂┼─┼─┼─┼─┼─┼─┼─┼─          
                     ┃                          
                    ├─┤                         
                     ↑                          
             1st cell vertical screen           
             scroll value valid area

The bit configuration of the vertical screen scroll value is the same as when setting it in each register. Also, the data in the vertical cell scroll table is arranged in order from the data for the cells on the left side of the TV screen.
When using the vertical cell scroll function for both NBG0 and NBG1, store each vertical cell scroll table data alternately, one cell at a time, for NBG0 and NBG1.

Figure 5.7 shows the bit configuration of vertical cell scroll table data, and Figure 5.8 shows the configuration of the vertical cell scroll table.

Figure 5.7 Data structure on vertical cell scroll table

●Vertical screen scroll value　
Bit F E D C B A 9 8 7 6 5 4 3 2 1 0　
   ┌─┬─┬─┬─┬─┰─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┐
+0H│−│−│−│−│−┃ Integer part        │
   │ │ │ │ │ ┃ (11 bits)           │
   └─┴─┴─┴─┴─┸─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┘
　
Bit F E D C B A 9 8 7 6 5 4 3 2 1 0　
   ┌─┬─┬─┬─┬─┬─┬─┬─┰─┬─┬─┬─┬─┬─┬─┬─┐
+2H│ Decimal part  ┃−│−│−│−│−│−│−│−│
   │ (8 bits)      ┃ │ │ │ │ │ │ │ │
   └─┴─┴─┴─┴─┴─┴─┴─┸─┴─┴─┴─┴─┴─┴─┴─┘
　
[Note] "-" is ignored

Figure 5.8 Vertical cell scroll table example

●When performing vertical cell scrolling only on NBG0　
                       Vertical cell scroll table (VRAM)   
                     MSB                                LSB
                    ┌─────────────────────────────────────┐
Vertical cell → +00H| Vertical screen scroll value of the |
scroll table        | 1st cell of NBG0 / Integer part     |
address             ├─────────────────────────────────────┤
                +02H| Vertical screen scroll value of the |
                    | 1st cell of NBG0 / Decimal part     |
                    ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
                +04H| Vertical screen scroll value of the |
                    | 2nd cell of NBG0 / Integer part     |
                    ├─────────────────────────────────────┤
                +06H| Vertical screen scroll value of the |
                    | 2nd cell of NBG0 / Decimal part     |
                    ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
                +08H| Vertical screen scroll value of     |
                    | 3rd cell of NBG0 / Integer part     |
                    ├─────────────────────────────────────┤
                +0AH| Vertical screen scroll value of     |
                    | 3rd cell of NBG0 / Decimal part     |
                    ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
                +0CH| Vertical screen scroll value of     |
                    | 4th cell of NBG0 / Integer part     |
                    ├─────────────────────────────────────┤
                +0EH| Vertical screen scroll value of     |
                    | 4th cell of NBG0 / Decimal part     |
                    ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
                +10H| Vertical screen scroll value of     |
                    | 5th cell of NBG0 / Integer part     |
                    ├─────────────────────────────────────┤
                +12H| Vertical screen scroll value of     |
                    | 5th cell of NBG0 / Decimal part     |
                    ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥

●When vertical cell scrolling is performed only in NBG1　
                       Vertical cell scroll table (VRAM)   
                     MSB                                LSB
                    ┌─────────────────────────────────────┐
Vertical cell → +00H| Vertical screen scroll value of the |
scroll table        | 1st cell of NBG1 / Integer part     |
address             ├─────────────────────────────────────┤
                +02H| Vertical screen scroll value of the |
                    | 1st cell of NBG1 / Decimal part     |
                    ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
                +04H| Vertical screen scroll value of the |
                    | 2nd cell of NBG1 / Integer part     |
                    ├─────────────────────────────────────┤
                +06H| Vertical screen scroll value of the |
                    | 2nd cell of NBG1 / Decimal part     |
                    ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
                +08H| Vertical screen scroll value of the |
                    | 3rd cell of NBG1 / Integer part     |
                    ├─────────────────────────────────────┤
                +0AH| Vertical screen scroll value of the |
                    | 3rd cell of NBG1 / Decimal part     |
                    ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
                +0CH| Vertical screen scroll value of the |
                    | 4th cell of NBG1 / Integer part     |
                    ├─────────────────────────────────────┤
                +0EH| Vertical screen scroll value of the |
                    | 4th cell of NBG1 / Decimal part     |
                    ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
                +10H| Vertical screen scroll value of the |
                    | 5th cell of NBG1 / Integer part     |
                    ├─────────────────────────────────────┤
                +12H| Vertical screen scroll value of the |
                    | 5th cell of NBG1 / Decimal part     |
                    ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥

●When vertical cell scrolling of NBG0 and NBG1　
                       Vertical cell scroll table (VRAM)   
                     MSB                                LSB
                    ┌─────────────────────────────────────┐
Vertical cell → +00H| Vertical screen scroll value of the |
scroll table        | 1st cell of NBG0 / Integer part     |
address             ├─────────────────────────────────────┤
                +02H| Vertical screen scroll value of the |
                    | 1st cell of NBG0 / Decimal part     |
                    ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
                +04H| Vertical screen scroll value of the |
                    | 1st cell of NBG1 / Integer part     |
                    ├─────────────────────────────────────┤
                +06H| Vertical screen scroll value of the |
                    | 1st cell of NBG1 / Decimal part     |
                    ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
                +08H| Vertical screen scroll value of the |
                    | 2nd cell of NBG0 / Integer part     |
                    ├─────────────────────────────────────┤
                +0AH| Vertical screen scroll value of the |
                    | 2nd cell of NBG0 / Decimal part     |
                    ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
                +0CH| Vertical screen scroll value of the |
                    | 2nd cell of NBG1 / Integer part     |
                    ├─────────────────────────────────────┤
                +0EH| Vertical screen scroll value of the |
                    | 2nd cell of NBG1 / Decimal part     |
                    ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥
                +10H| Vertical screen scroll value of the |
                    | 3rd cell of NBG0 / Integer part     |
                    ├─────────────────────────────────────┤
                +12H| Vertical screen scroll value of the |
                    | 3rd cell of NBG0 / Decimal part     |
                    ┝━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┥

●Line & vertical cell scroll control register

The line & vertical cell scroll control register controls the line scroll function and vertical cell scroll function. This is a 16-bit write-only register located at address 18009AH. The value is cleared to 0 after power-on or reset, so be sure to set it.

SCRCTL 18009AH

-	-	N1LSS1	N1LSS0	N1LZMX	N1LSCY	N1LSCX	N1VCSC
15	14	13	12	11	10	09	08

07
06
05
04
03
02
01
00

-
-
N0LSS1
N0LSS0
N0LZMX
N0LSCY
N0LSCX
N0VCSC

Line scroll interval bit : Line scroll select bit (N0LSS1, N0LSS0, N1LSS1, N1LSS0)

07	06	05	04	03	02	01	00
-	-	N0LSS1	N0LSS0	N0LZMX	N0LSCY	N0LSCX	N0VCSC

Specify the interval at which line scroll table data is read from the table. The interval changes depending on the TV screen's interlace settings.

N0LSS1,N0LSS0	18009AH	bit 5,4	For NBG0
N1LSS1,N1LSS0	18009AH	bit 13,12	For NBG1

NxLSS1	NxLSS0	Interlace settings
NxLSS1	NxLSS0	non-interlaced	Single dense interlace	double dense interlace
0	0	per line	every 2 lines	per line
0	1	every 2 lines	every 4 lines	every 2 lines
1	0	every 4 lines	every 8 lines	every 4 lines
1	1	every 8 lines	every 16 lines	every 8 lines

[Note] 0 or 1 is entered for x in the bit name.

When reading line scroll table data at intervals of two or more lines, the previously read line scroll data is used for the horizontal screen scroll value and horizontal coordinate increment of the line that is not read. Also, the vertical screen scroll value is calculated from the previously read line scroll data and the value of the vertical coordinate increment register.

Line zoom X enable bit (N1LZMX, N0LZMX)

Specifies whether to scale horizontally in units of lines.

N0LZMX	18009AH	bit 3	For NBG0
N1LZMX	18009AH	bit 11	For NBG1

NxLZMX	process
0	Does not scale horizontally in units of lines
1	Scale horizontally in units of lines

[Note] 0 or 1 is entered for x in the bit name.

When using this feature, be sure to store the horizontal coordinate increments in the VRAM line scroll table. Make sure that the horizontal coordinate increment does not exceed the scale setting.

Line scroll enable bit (for vertical screen scroll value) : Line scroll Y enable bit

(N1LSCY, N0LSCY)
Specifies whether to scroll vertically by line.

N0LSCY	18009AH	bit 2	For NBG0
N1LSCY	18009AH	bit 10	For NBG1

NxLSCY	process
0	Do not scroll vertically by line
1	Scroll vertically line by line

[Note] 0 or 1 is entered for x in the bit name.

When using this feature, be sure to store the vertical screen scroll value in the VRAM line scroll table.

Line scroll enable bit (for horizontal screen scroll value) : Line scroll X enable bit

(N1LSCX, N0LSCX)
Specifies whether to scroll horizontally by line.

N0LSCX	18009AH	bit 1	For NBG0
N1LSCX	18009AH	bit 9	For NBG1

NxLSCX	process
0	Do not scroll horizontally by line
1	Scroll horizontally line by line

[Note] 0 or 1 is entered for x in the bit name.

When using this feature, be sure to store the horizontal screen scroll value in the VRAM line scroll table.

Vertical cell scroll enable bit : Vertical cell scroll enable bit

(N1VCSC, N0VCSC)
Specify whether to perform vertical cell scrolling.

N0VCSC	18009AH	bit 0	For NBG0
N1VCSC	18009AH	bit 8	For NBG1

NxVCSC	process
0	Does not perform vertical cell scrolling
1	Performs vertical cell scrolling

[Note] 0 or 1 is entered for x in the bit name.

When using the vertical cell scroll function, be sure to specify the vertical cell scroll table data read access command in the VRAM cycle pattern register. Also, be sure to store vertical cell scroll data in VRAM.
The vertical cell scrolling function cannot be used at the same time as the mosaic function, and the mosaic function takes precedence.

Limitations of vertical scrolling function

	Limitations of vertical scrolling function

When changing the state in which the vertical cell scroll function is used (ON) to the state in which it is not used (OFF), that is, when changing the vertical cell scroll enable bit (N0VCSC, N1VCSC) from "1" to "0", the VRAM cycle pattern register The access command (Ch or Dh) for vertical cell scroll table data read for NBG0 or NBG1 that is set to , must also be changed to an access command (Fh) that says " do not access " during the same V blank period.

This restriction must also be observed when changing from using the vertical cell scrolling functions of NBG0 and NBG1 at the same time to not using either of the vertical cell scrolling functions.

Examples of restrictions

Example 1: When using NBG0's vertical cell scrolling function

If the settings when using the vertical cell scrolling function are as follows:

＜ setting＞

Vertical cell scroll enable bit for NBG0 (N0VCSC) = 1
VRAM cycle pattern register (CYCA0L) = C 0FFh

To disable the vertical cell scrolling function of NBG0 from this state, change the settings as follows during the same V blank period.

＜ setting＞

Vertical cell scroll enable bit for NBG0 (N0VCSC) = 0
VRAM cycle pattern register (CYCA0L) = F 0FFh

Example 2: When using the vertical cell scrolling functions of NBG0 and NBG1 at the same time

If the settings when using the vertical cell scrolling function are as follows:

＜ setting＞

Vertical cell scroll enable bit for NBG0 (N0VCSC) = 1
Vertical cell scroll enable bit for NBG1 (N1VCSC) = 1
VRAM cycle pattern register (CYCA0L) = C D 01h

To change from this state to a state where only the vertical cell scroll function of NBG1 is not used, change the settings as follows during the same V blank period.

＜ setting＞

Vertical cell scroll enable bit for NBG0 (N0VCSC) = 1
Vertical cell scroll enable bit for NBG1 (N1VCSC) = 0
VRAM cycle pattern register (CYCA0L) = C F 01h

●Line scroll table address register

The line scroll table address register specifies the start address of the line scroll table. This is a 32-bit write-only register located at addresses 1800A0H to 1800A6H. The value is cleared to 0 after power-on or reset, so be sure to set it.

LSTA0U 1800A0H

-	-	-	-	-	-	-	-
15	14	13	12	11	10	09	08

07
06
05
04
03
02
01
00

-
-
-
-
-
N0LSTA18
N0LSTA17
N0LSTA16

07	06	05	04	03	02	01	00
-	-	-	-	-	N0LSTA18	N0LSTA17	N0LSTA16

LSTA0L 1800A2H

N0LSTA15	N0LSTA14	N0LSTA13	N0LSTA12	N0LSTA11	N0LSTA10	N0LSTA9	N0LSTA8
15	14	13	12	11	10	09	08

07
06
05
04
03
02
01
00

N0LSTA7
N0LSTA6
N0LSTA5
N0LSTA4
N0LSTA3
N0LSTA2
N0LSTA1
-

07	06	05	04	03	02	01	00
N0LSTA7	N0LSTA6	N0LSTA5	N0LSTA4	N0LSTA3	N0LSTA2	N0LSTA1	-

LSTA1U 1800A4H

-	-	-	-	-	-	-	-
15	14	13	12	11	10	09	08

07
06
05
04
03
02
01
00

-
-
-
-
-
N1LSTA18
N1LSTA17
N1LSTA16

07	06	05	04	03	02	01	00
-	-	-	-	-	N1LSTA18	N1LSTA17	N1LSTA16

LSTA1L 1800A6H

N1LSTA15	N1LSTA14	N1LSTA13	N1LSTA12	N1LSTA11	N1LSTA10	N1LSTA9	N1LSTA8
15	14	13	12	11	10	09	08

07
06
05
04
03
02
01
00

N1LSTA7
N1LSTA6
N1LSTA5
N1LSTA4
N1LSTA3
N1LSTA2
N1LSTA1
-

Line scroll table address bit : Line scroll table address bit

07	06	05	04	03	02	01	00
N1LSTA7	N1LSTA6	N1LSTA5	N1LSTA4	N1LSTA3	N1LSTA2	N1LSTA1	-

(N0LSTA18~N0LSTA16, N0LSTA15~N0LSTA1, N1LSTA18~N1LSTA16, N1LSTA15~N1LSTA1)
Specify the start address of the line scroll table on VRAM.

N0LSTA18～N0LSTA16 1800A0H bits 2-0 For NBG0 (upper bit)

N0LSTA15～N0LSTA1 1800A2H bits 15 to 1 For NBG0 (lower bit)

N1LSTA18~N1LSTA16 1800A4H bits 2-0 For NBG1 (upper bit)

N1LSTA15～N1LSTA1 1800A6H bits 15 to 1 For NBG1 (lower bit)

The actual first VRAM address is calculated using the following formula: If the VRAM capacity is 4Mbits, the most significant bit of the address is ignored.

 (Line scroll table start address) = (Line scroll table address register value 18 bits) x 4H

●Vertical cell scroll table address register

The vertical cell scroll table address register specifies the start address of the vertical cell scroll table. This is a 32-bit write-only register located at addresses 18009CH to 18009EH. The value is cleared to 0 after power-on or reset, so be sure to set it.

VCSTAU 18009CH

-	-	-	-	-	-	-	-
15	14	13	12	11	10	09	08

07
06
05
04
03
02
01
00

-
-
-
-
-
VCSTA18
VCSTA17
VCSTA16

07	06	05	04	03	02	01	00
-	-	-	-	-	VCSTA18	VCSTA17	VCSTA16

VCSTAL 18009EH

VCSTA15	VCSTA14	VCSTA13	VCSTA12	VCSTA11	VCSTA10	VCSTA9	VCSTA8
15	14	13	12	11	10	09	08

07
06
05
04
03
02
01
00

VCSTA7
VCSTA6
VCSTA5
VCSTA4
VCSTA3
VCSTA2
VCSTA1
-

Vertical cell scroll table address bit : Vertical cell scroll table address bit (VCSTA18 to VCSTA1)

07	06	05	04	03	02	01	00
VCSTA7	VCSTA6	VCSTA5	VCSTA4	VCSTA3	VCSTA2	VCSTA1	-

Specify the start address of the vertical cell scroll table on VRAM.

VCSTA18~VCSTA16	18009CH	bits 2-0
VCSTA15~VCSTA1	18009EH	bits 15 to 1

The actual first VRAM address is calculated using the following formula: If the VRAM capacity is 4Mbits, the most significant bit of the address is ignored.

(vertical cell scroll table start address) = (vertical cell scroll table address register value 18 bits) x 4H

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★ HARDWARE Manual VDP2 User's Manual ★ Chapter 5 Normal scroll screen

N0LSTA18～N0LSTA16	1800A0H	bits 2-0	For NBG0 (upper bit)
N0LSTA15～N0LSTA1	1800A2H	bits 15 to 1	For NBG0 (lower bit)
N1LSTA18~N1LSTA16	1800A4H	bits 2-0	For NBG1 (upper bit)
N1LSTA15～N1LSTA1	1800A6H	bits 15 to 1	For NBG1 (lower bit)