- If the dot color data of the sprite and each scroll screen is in palette format, the color RAM address is the dot color data made up of the palette number and dot color code, plus the value of the color RAM address offset register, and the address of that address is Outputs color data as dot color data. In the case of RGB format, the dot color data consisting of each RGB data is output as is as the color data of that dot.
If the dot color data on the scroll screen is in palette format, you can specify whether to use the special priority function or special color calculation function by the value of the lower 4 bits of the dot color data.
■10.1 Dot color data in palette format
- Dot color data in palette format is 11-bit data, and the value of the color RAM address offset register of the corresponding screen is added to the upper 3 bits to determine the color RAM address that stores the color data of that dot.
●Sprite dot color data
- Sprite dot color data in palette format varies depending on the specified sprite type. If you specify a sprite type with dot color data of 10 bits or less, fix the missing high-order bits to 0, add the color RAM address offset value for the sprite to the high-order 3 bits, and set the color RAM address of that dot. will do. Note that if the color RAM mode is set to mode 0 or mode 2, the most significant bit of the color RAM address is ignored.
- Figure 10.1 shows the sprite dot color data in palette format, and Figure 10.2 shows the sprite color RAM address.
- Figure 10.1 Sprite dot color data in palette format
- ◆For sprite types 0 to 3, 5
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Dot color data 11 bits |
|---|
- ◆For sprite types 4 and 6
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Dot color data 10 bits |
|---|
- ◆For sprite type 7
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | Dot color data 9 bits |
|---|
- ◆For sprite types C to F
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | Dot color data 8 bits |
|---|
- ◆For sprite type 8
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | Dot color data 7 bits |
|---|
- ◆For sprite types 9 to B
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | Dot color data 6 bits |
|---|
- Figure 10.2 Sprite color RAM address
- ・Sprite dot color data
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Dot color data 11 bits |
|---|
- ・Color RAM address offset for sprites
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Offset value
3 bits | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|---|
- ・Color RAM address of that dot
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Color RAM address 11 bits |
|---|
- [note]
- If the color RAM mode is mode 0 or mode 2 , the most significant bit (LSB) of the color RAM address is ignored.
●Scroll dot color data
- Scroll dot color data in palette format varies depending on the number of specified character colors. Add the color RAM address offset value corresponding to each side to the upper 3 bits of the 11-bit dot color data to determine the color RAM address of that dot. Note that if the color RAM mode is set to mode 0 or mode 2, the most significant bit of the color RAM address is ignored.
- Line color screens do not have a corresponding color RAM address offset value, so the 11-bit value read from the line color screen table becomes the color RAM address.
- Figure 10.3 shows the scroll dot color data in palette format, and Figure 10.4 shows the color RAM address for the scroll screen.
- Figure 10.3 Scroll dot color data in palette format
- ◆When the number of character colors is 16
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
pallet number
7 bit | dot color code
4 bits |
|---|
- ◆When the number of character colors is 256
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
palette
number
3 bits | dot color code
8 bit |
|---|
- ◆When the number of character colors is 2048 colors
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
dot color data
11 bit |
|---|
- Figure 10.4 Scroll color RAM address
- ・Scroll dot color data
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Dot color data 11 bits |
|---|
- ・Color RAM address offset for each scroll
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Offset value
3 bits | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|---|
- ・Color RAM address of that dot
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Color RAM address 11 bits |
|---|
- [note]
- If the color RAM mode is mode 0 or mode 2 , the most significant bit (LSB) of the color RAM address is ignored.
●Color RAM address offset register
- The color RAM address offset register specifies the color RAM address offset value for the sprite and each scroll screen. This is a 16-bit write-only register located at addresses 1800E4H to 1800E6H. The value is cleared to 0 after power-on or reset, so be sure to set it.
- CRAOFA 1800E4H
- CRAOFB 1800E6H
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 |
- | - | - | - | - | - | - | - |
|---|
- Color RAM address offset bit : Color RAM address offset bit
- (N0CAOS2~N0CAOS0, N1CAOS2~N1CAOS0, N2CAOS2~N2CAOS0, N3CAOS2~N3CAOS0, R0CAOS2~R0CAOS0, SPCAOS2~SPCAOS0)
Specifies the color RAM address offset value for the sprite and each scroll screen.
| N0CAOS2〜N0CAOS0 | 1800E4H | bits 2-0 | For NBG0 (or for RBG1) |
| N1CAOS2～N1CAOS0 | 1800E4H | bits 6-4 | For NBG1 (or for EXBG) |
| N2CAOS2～N2CAOS0 | 1800E4H | bits 10-8 | For NBG2 |
| N3CAOS2～N3CAOS0 | 1800E4H | bits 14-12 | For NBG3 |
| R0CAOS2〜R0CAOS0 | 1800E6H | bits 2-0 | For RBG0 |
| SPCAOS2～SPCAOS0 | 1800E6H | bits 6-4 | for sprites |
- The actual color RAM address offset value is calculated using the following formula: If the color RAM mode is mode 0 or mode 2, the most significant bit of the color RAM address resulting from adding the color RAM address offset value is ignored.
- ・When the color RAM mode is mode 0 or mode 1
(Color RAM address offset value)
= (Color RAM address offset register value 3 bits) x 200H
- ・When the color RAM mode is mode 2
(Color RAM address offset value)
= (Color RAM address offset register value 3 bits) x 400H
