2.2 Data specifications

[Low level SCU]

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Title data specifications

Data DMA channel

Data name none

No 1

Use the following constants when specifying the SCU's DMA channel:

constant	explanation
DMA_SCU_CH0	channel 0
DMA_SCU_CH1	channel 1
DMA_SCU_CH2	channel 2

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Title data specifications

Data Transfer parameters

Data name DmaScuPrm

No 2

The transfer parameter is a structure like the one below.

struct {
     Uint32 dxr; /* Read address */
     Uint32 dxw; /* Export address */
     Uint32 dxc; /* Number of transferred bytes */
     Uint32 dxad_r; /* Read address addition value */
     Uint32 dxad_w; /* Write address addition value */
     Uint32 dxmod; /* mode bit */
     Uint32 dxrup; /* Read address update bit */
     Uint32 dxwup; /* Write address update bit */
     Uint32 dxft; /* Activation factor selection bit */
     Uint32 msk; /* mask bit */
}DmaScuPrm;

The following are constants that can be used with each member.

dxad_r /* Read address addition value */

constant	explanation
DMA_SCU_R0	do not add
DMA_SCU_R4	Add 4 bytes

dxad_w /* Write address addition value */

constant	explanation
DMA_SCU_W0	do not add
DMA_SCU_W2	Add 2 bytes
DMA_SCU_W4	Add 4 bytes
DMA_SCU_W8	Add 8 bytes
DMA_SCU_W16	Add 16 bytes
DMA_SCU_W32	Add 32 bytes
DMA_SCU_W64	Add 64 bytes
DMA_SCU_W128	Add 128 bytes

dxmod /* mode bit */

constant	explanation
DMA_SCU_DIR	direct mode
DMA_SCU_IN_DIR	indirect mode

dxrup /* Read address update bit */
dxwup /* Write address update bit */

constant	explanation
DMA_SCU_KEEP	Hold
DMA_SCU_REN	Update

dxft /* Activation factor selection bit */

constant	explanation
DMA_SCU_F_VBLK_IN	V-blank-IN signal reception
DMA_SCU_F_VBLK_OUT	V-blank-OUT signal reception
DMA_SCU_F_HBLK_IN	H-Blank-IN signal reception
DMA_SCU_F_TIM0	Timer 0 signal received
DMA_SCU_F_TIM1	Timer 1 signal reception
DMA_SCU_F_SND	Sound-Req signal reception
DMA_SCU_F_SPR	Sprite drawing end signal received
DMA_SCU_F_DMA	Setting the DMA activation factor bit

mask /* mask bit */

Member write mask bits. Bits other than those specified by the constants below are not written (set). Multiple specifications can be specified by logical sum.

constant	explanation
DMA_SCU_M_DXR	read address
DMA_SCU_M_DXW	Export address
DMA_SCU_M_DXC	Number of bytes transferred
DMA_SCU_M_DXAD_R	Read address addition value
DMA_SCU_M_DXAD_W	Write address addition value
DMA_SCU_M_DXMOD	mode bit
DMA_SCU_M_DXRUP	Read address update bit
DMA_SCU_M_DXWUP	Write address update bit
DMA_SCU_M_DXFT	Activation factor selection bit

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Title data specifications

Data status

Data name DmaScuStatus

No 3

The status is a structure like the following.

struct {
    	Uint32dxmv;
        }

The following are constants that can be used with each member.

dxmv /* DMA operation flag */

constant	explanation
DMA_SCU_MV	in action
DMA_SCU_NO_MV	not working

[Low level CPU]

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Title data specifications

Data DMA channel

Data name none

No 4

Use the following constants when specifying the CPU's DMA channel:

constant	explanation
DMA_CPU_CH0	channel 0
DMA_CPU_CH1	channel 1

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Title data specifications

Data Common transfer parameters

Data name DmaCpuComPrm

No 5

The common transfer parameter is a structure like the one below.

struct {
     Uint32 pr; /* Priority mode */
     Uint32 dme; /* DMA master enable */
     Uint32 msk; /* mask bit */
}DmaCpuComPrm;

The following are constants that can be used with each member.

pr /* priority mode */

constant	explanation
DMA_CPU_FIX	Fixed priority
DMA_CPU_ROR	Priority is determined by round robin

 dme /* DMA master enable */

constant	explanation
DMA_CPU_DIS	Disable DMA transfer for all channels
DMA_CPU_ENA	Allow DMA transfer for all channels

 msk /* mask bit */

Member write mask bits. Bits other than those specified by the constants below are not written (set). Multiple specifications can be specified by logical sum.

constant	explanation
DMA_CPU_M_PR	priority mode
DMA_CPU_M_AE	address error flag
DMA_CPU_M_NMIF	NMI flag
DMA_CPU_M_DME	DMA master enable

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Title data specifications

Data Transfer parameters

Data name DmaCpuPrm

No 6

The transfer parameter is a structure like the one below.

struct {
     Uint32 sar; /* DMA source address */
     Uint32 dar; /* DMA destination address */
     Uint32 tcr; /* DMA transfer count */
     Uint32 dm; /* Destination address mode */
     Uint32 sm; /* Source address mode bit */
     Uint32 ts; /* Transfer size */
     Uint32 ar; /* Auto request mode */
     Uint32 ie; /* Interrupt enable */
     Uint32 drcr; /* DMA request/response selection control */
     Uint32 msk; /* mask bit */
}DmaCpuPrm;

The following are constants that can be used with each member.

dm /* destination address mode */
sm /* Source address mode bit */

constant	explanation
DMA_CPU_AM_NOM	fixed
DMA_CPU_AM_ADD	increase
DMA_CPU_AM_SUB	decrease

ts /* Transfer size */

constant	explanation
DMA_CPU_1	Byte unit
DMA_CPU_2	Word (2 bytes) unit
DMA_CPU_4	Longword (4 bytes) unit
DMA_CPU_16	16 byte unit

 ar /* Auto request mode */

constant	explanation
DMA_CPU_MOD	module request
DMA_CPU_AUTO	art request

 ie /* interrupt enable */

constant	explanation
DMA_CPU_INT_ENA	Allow interrupt requests
DMA_CPU_INT_DIS	Disable interrupt requests

 drcr /* DMA request/response selection control */

constant	explanation
DMA_CPU_DREQ	DREQ (external request)
DMA_CPU_RXI	RXI (Built-in SCI receive data full interrupt transfer request)
DMA_CPU_TXI	TXI (Built-in SCI transmit data empty interrupt transfer request)

 msk /* mask bit */

Member write mask bits. Bits other than those specified by the constants below are not written (set). Multiple specifications can be specified by logical sum.

constant	explanation
DMA_CPU_M_SAR	DMA source address
DMA_CPU_M_DAR	DMA destination address
DMA_CPU_M_TCR	DMA transfer count
DMA_CPU_M_DM	Destination address mode
DMA_CPU_M_SM	Source address mode bit
DMA_CPU_M_TS	transfer size
DMA_CPU_M_AR	auto request mode
DMA_CPU_M_IE	interrupt enable
DMA_CPU_M_DRCR	DMA request/response selection control
DMA_CPU_M_TE	transfer end flag