2.Reference

2.1 Data list

data		data name	number
Interrupt register access management
	Interrupt mask bit value constant	none	1
	Interrupt status bit value constant	none	2
Registering and referencing interrupt processing routines
	vector number constant	none	3

2.2 Data specifications

[Interrupt register access management]

one View table

Title data specifications

Data Interrupt mask bit value constant

Data name none

No 1

The constants that can be set as interrupt mask bit values are shown below. The value of each constant is set to 1 for the 1 bit indicated by the constant and 0 for the other bits. Multiple settings can be made at once by logical sum.

constant name	explanation
INT_MSK_NULL	unspecified
INT_MSK_ALL	Full specification (specify all bits shown below)
INT_MSK_ABUS	A-Bus
INT_MSK_SPR	Sprite drawing finished
INT_MSK_DMAI	DMA illegal
INT_MSK_DMA0	Level 0-DMA
INT_MSK_DMA1	Level 1-DMA
INT_MSK_DMA2	Level 2-DMA
INT_MSK_PAD	P.A.D.
INT_MSK_SYS	system manager
INT_MSK_SND	sound request
INT_MSK_DSP	DSP end
INT_MSK_TIM1	timer-1
INT_MSK_TIM0	timer-0
INT_MSK_HBLK_IN	H-blank-IN
INT_MSK_VBLK_OUT	V-blank-OUT
INT_MSK_VBLK_IN	V-blank-IN

one View table

Title data specifications

Data Interrupt status bit value constant

Data name none

No 2

The constants that can be set to interrupt status bit values are shown below. The value of each constant is set to 1 for the 1 bit indicated by the constant and 0 for the other bits. Multiple settings can be made at once by logical sum.

constant name	explanation
INT_ST_NULL	unspecified
INT_ST_ALL	Full specification (specify all bits shown below)
INT_ST_ABUS	A-Bus (specify bits of A-Bus01 to 16)
INT_ST_ABUS01~16	A-Bus01~16
INT_ST_SPR	Sprite drawing finished
INT_ST_DMAI	DMA illegal
INT_ST_DMA0	Level 0-DMA
INT_ST_DMA1	Level 1-DMA
INT_ST_DMA2	Level 2-DMA
INT_ST_PAD	P.A.D.
INT_ST_SYS	system manager
INT_ST_SND	sound request
INT_ST_DSP	DSP end
INT_ST_TIM1	timer-1
INT_ST_TIM0	timer-0
INT_ST_HBLK_IN	H-blank-IN
INT_ST_VBLK_OUT	V-blank-OUT
INT_ST_VBLK_IN	V-blank-IN

[Register and reference interrupt handling routine]

one View table

Title data specifications

Data vector number constant

Data name none

No 3

The constants that can be set for vector numbers are shown below. SCU constant names can only be set on master SH2.
CPU constant names can be set on master and slave SH2.

Interrupt classification	constant name	explanation
SCU	INT_SCU_ABUS	A-Bus
	INT_SCU_SPR	Sprite drawing finished
	INT_SCU_DMAI	DMA illegal
	INT_SCU_DMA0	Level 0-DMA
	INT_SCU_DMA1	Level 1-DMA
	INT_SCU_DMA2	Level 2-DMA
	INT_SCU_PAD	P.A.D.
	INT_SCU_SYS	system manager
	INT_SCU_SND	sound request
	INT_SCU_DSP	DSP end
	INT_SCU_TIM1	timer-1
	INT_SCU_TIM0	timer-0
	INT_SCU_HBLK_IN	H-blank-IN
	INT_SCU_VBLK_OUT	V-blank-OUT
	INT_SCU_VBLK_IN	V-blank-IN
CPU	INT_CPU_DIVU	divider
	INT_CPU_DMAC0	DMAC channel 0
	INT_CPU_DMAC1	DMAC channel 1
	INT_CPU_WDT	WDT interval
	INT_CPU_BSC	BSC compare match
	INT_CPU_SCI_ERI	SCI reception error
	INT_CPU_SCI_RXI	SCI receive data full
	INT_CPU_SCI_TXI	SCI receive data empty
	INT_CPU_SCI_TEI	SCI transmission finished
	INT_CPU_FRT_ICI	FRT input capture
	INT_CPU_FRT_OCI	FRT output compare
	INT_CPU_FRT_OVI	FRT overflow