guide

■Explanation

●Register/reference operations for interrupt processing routines

After booting from BOOT ROM, the interrupt vector table of master SH2 is located at the beginning of work RAM, and VBR (vector base register) points to this address.
The slave SH2's interrupt vector table is at the beginning of work RAM + 400H, and the slave SH2's VBR points to that address.

By default, the interrupt vectors (programmable) for each SH2 built-in module are assigned as shown in the table below. Additionally, a dummy routine is set in the vector table that does nothing. (However, illegal instruction and address error exceptions are infinite loops.)

The FRT input capture interrupt is assigned for master-slave communication, and its initial priority is 15 (highest priority).

In the table below, the priority of each interrupt except the FRT input capture interrupt is set to 0, and interrupts are not allowed.
To change the interrupt priority of an on-chip module, the contents of the interrupt control register must be changed according to the needs of the application.

Master SH2 vector initial setting	Slave SH2 vector initial settings
40H~SCU interrupt vector 5FH (fixed by hardware)	41H H Blank In ** 43H V blank In
60H SCI reception error 61H SCI receive buffer full 62H SCI transmit buffer empty 63H SCI transmission finished * 64H FRT input capture 65H FRT compare match 66H FRT overflow 67H unused 68H WDT interval 69H BSC compare match 6AH unused 6BH unused 6CH DMACH1 (Built-in SH2) 6DH DMACH0 (Built-in SH2) 6EH DIVU (division) 6FH Not used	60H SCI reception error 61H SCI receive buffer full 62H SCI transmit buffer empty 63H SCI transmission completed * 64H FRT input capture 65H FRT compare match 66H FRT overflow 67H unused 68H WDT interval 69H BSC compare match 6AH unused 6BH unused 6CH DMACH1 (Built-in SH2) 6DH DMACH0 (Built-in SH2) 6EH DIVU (division) 6FH Not used
* For slave → master passing	* For master → slave passing ** IRL2, IRL6 level interrupt

Use this operation routine to register an interrupt processing routine to an interrupt vector or refer to the current processing routine address.
For SCU interrupts on the master side, an SCU interrupt routine is provided that implements interrupt processing by calling a subroutine of a C function, and you can also register a C function there and refer to its registered address. Masu.

The functions registered in the SCU interrupt routine will be called every time an interrupt occurs. Before and after that call, save and restore registers according to the SHC compiler's register saving rules. Therefore, any C function or routine that follows its rules can be registered and processed. However, it may not be suitable for interrupt processing that requires a fast response, such as H blank In.
If you register another interrupt handling routine to the SCU interrupt vector, the SCU interrupt handling routine will be bypassed and disabled.

●Set/reference/change operation of SCU interrupt mask

The mask value set in the SCU interrupt mask register cannot be read, so if you change it, you will not be able to perform calculations on the value that is actually set.
To this end, we store this value separately in memory and provide a service routine that updates it consistently with the actual SCU interrupt mask register.
When used, libraries and applications must always set and change the SCU interrupt mask via these functions.
Furthermore, after setting or changing the SCU interrupt mask register, clear the SCU interrupt status register and, if necessary, clear the A-Bus interrupt acknowledge register.

●Simple semaphore operation

We provide a service that allows you to use the memory (256 bytes) provided by BOOT ROM as 256 simple semaphores.
The first half of the semaphore (numbers 0 to 127) can be used freely. The second half (128-255) is for operations related to libraries.
When a library uses a particular feature, such as DMA, it sets the semaphore's MSB (80H) to 1 to indicate that it is in use. It also clears the MSB after use, indicating it is free.
Normally, in processes that take a relatively long time and require resources to be secured, procedures for manipulating and referencing semaphores should be determined to prevent interrupt processes that occur during the process from accessing those resources without permission.
The SH2 TAS instruction is used to set the MSB for semaphore memory. This instruction is atomic (does not release bus ownership), so only one process can acquire the semaphore.
Once you have completed the process that acquired the semaphore, you must release it.
At reset, all semaphore memory is released (cleared).

●System clock switching

System clock switching cannot be done by issuing a single command to SMPC. Use of this system program is required.

• CPU clock 26MHz ←→ 28MHz
• Horizontal resolution 320/640 ←→ 352/704

Switching the system clock involves resetting some hardware.

Device being reset	OFF or non-warranty device	Unaffected devices
SCU VDP1 VDP2 SCSI/SCC (development machine only)	Slave SH (OFF) DRAM (previous contents destroyed) SCSP(OFF)	Master SH *Note SDRAM CD SIMM (development machine only)

*note

Since the master SH goes into standby mode during clock switching, the FRT and SCI of the SH built-in modules will need to be reconfigured. Note that WDT is used in this process. Also, after processing, the state will be the same as the NMI, for example, DMAC control will be suspended due to the NMI. Please refer to the SH manual and take steps to restart processing if necessary.

About reinitialization process after reset

SCU・・・・・・

Reinitialize bus, interrupt mask, etc. However, the value of SYS_GETSCUIM is used for the interrupt mask value.

About post-processing required by the application

VDP2・・・・・・

You need to set the TV mode relatively quickly. Since the device itself will be in 320/640 mode after being reset, especially if you change the system clock to 352/704 mode, the synchronization signal may be out of sync with the TV and the screen may be distorted.

VDP1,2&SCSP・・・・・・

All previous settings are invalid. Reconfiguration is required.

SMPC・・・・・・

Hot reset is always enabled.

The processing time for clock change is approximately 110ms. This is because it includes device reset time.

●SCU interrupt routine priority change

The BOOT ROM has an interrupt priority management table for the SCU interrupt processing service, and also allows it to be rewritten.

	This is a dangerous service and can hang the system if there are priority conflicts in the table contents! ! !

This allows interrupt handling (using SYS_SETUINT) to be optimized for the application.
To do this, the application should prepare data with the same structure as the table and call SYS_CHGUIPR .
The table has 32 longwords, where 1 longword has the following content:

SH2 SR lower word value

SCU interrupt mask lower word value

Value set in SR when interrupt processing starts

At the start of interrupt processing, the value that is ORed with the current mask setting value and written to the SCU interrupt mask register.

The position of this longword in the table corresponds to the 30 interrupt sources of the SCU.
(V-Blank In is the first, V-Blank Out is the second...However, including the two longword spaces corresponding to vectors 4EH and 4FH)
In reality, you must take the utmost care to create a table so that the SR and SCU interrupt masks and interrupt sources are consistent.
For example, BOOT ROM has the following table as its initial settings.

Uint32 PRITab[32]={ 0x00F0FFFF, /*VBI SR=15 Totally prohibited (highest priority) 0x00E0FFFE, /*VBO SR=14 Only VBI allowed 0x00D0FFFC, /*HBI SR=13 Allow VBI, VBO ・ ・ 0x0070FE00 /*External 15 SR=7 Masks all SCU interrupts with inherent priority of 7 and below /*The A bus interrupt specific priorities are 7, 4, and 1 for each factor, but they are shared and set to 7 for 1-bit masking. };

*/ */ */ */ */

As a creation example, the SR value is always set to 0 and the priority (priority relationship) is described using only the SCU mask value. In this case, SH is always able to accept interrupts, and only the SCU mask controls whether to enable or disable them.

Uint32 PRITab[32]={ 0x0000FFF9, /*VBI processing, HBI, VBO allowed 0x0000FFFB, /*While processing VBO, only HBI is allowed 0x0000FFFF, /*Prohibit all during HBI processing (highest priority) ・ ・ 0x00000000 /*Allow all while processing external 15 (lowest priority) };

*/ */ */ */

Contrary to the above example, masking interrupts at the SR value level without changing the SCU mask value is prohibited! ! ! (only 0 or 15 possible)

In the example above, enabling and disabling interrupts for SH built-in modules requires manipulating the interrupt enable and disable registers for each built-in module.

When an interrupt from a certain source in the SCU is enabled and that interrupt occurs, the SR mask of the SH is higher than the specific level of that interrupt (value determined by the SCU hardware), and the interrupt is rejected by the SH. It's OK if the situation you're in is never possible. (However, as an exception, it is possible to completely ban SR Mask 15)

●Start CD multiplayer

This is a service that starts and runs the CD multiplayer when the application closes. When this service is called, regardless of the state in which it is called, the CD multiplayer screen will be displayed and operations will be available, exactly the same as when starting the power-on sequence.
It does not return to the caller.

●Power-on clear memory operation

Provides 8 bytes of memory on SDRAM managed by BOOT ROM.
These 8 bytes are initialized to 0 at power-on startup, but the contents are retained when the reset button (NMI) is pressed.