DMA instructions

DMA D0,[RAM],SImm

DMA transfer (D0[31-0]→RAM)

Operation details

Transfer D0[31-0] data to RAM. The external address register and transfer word count register are updated (added) according to the number of address additions. The transfer word count register is a register that stores the number of transfer words in longword units. Transfer ends when this word count becomes 0 or when the transfer is forcibly terminated.

descriptive formula

label: DMA D0,[Destination],Counter

Source=M0～M3 *

instruction code

31			28											17	16	15						９	８	７							０
１	１	０	０	−	−	−	−	−	−	−	−	−	−	ｘ	ｘ	ｘ	０	０	０	０	０	ｘ	ｘ
1	1	0	0	−	−	−	−	−	−	−	−	−	−	x	x	x	0	0	0	0	0	x	x	imm data

bit data Addition mode options bit17 bit16 bit15 0 0 0 Address addition 0 0 0 1 Address addition 1 0 1 0 Address addition 2 0 1 1 Address addition 4 1 0 0 Address addition 8 1 0 1 Address addition 16 1 1 0 Address addition 32 1 1 1 Address addition 64

bit data choices bit9 bit8 0 0 DATA RAM0 0 1 DATA RAM1 1 0 DATA RAM2 1 1 DATA RAM3

flag

It will be T0;1. **

remarks

* [Mx(x=0~3)] selects DATA RAMx(x=0~3).

** When the END signal indicating the end of transfer from the outside is received, it becomes T0;0.

To specify address addition, add the addition number after the instruction, and specify DMA0 to DMA64.

If address addition number specification is omitted, the addition number will be 1.

DMA [RAM],D0,SImm

DMA transfer (RAM→D0[31-0])

Operation details

Transfer RAM data to D0[31-0]. The external address register and transfer word count register are updated (added) according to the number of address additions. However, only addition numbers 0 and 1 are valid for A-Bus, and the writing unit is 32 bits. For B-Bus, all (addition numbers 0-64) are valid. The export unit will be 16 bits, and the 32 bit data will be divided into two and exported at intervals of 16 bits x (0-64). The transfer word count register is a register that stores the number of transfer words in longword units. Transfer ends when this word count becomes 0 or when the transfer is forcibly terminated.

descriptive formula

label: DMA [Source],D0,Counter

Source=M0～M3 *

instruction code

31			28											17	16	15						９	８	７							０
１	１	０	０	−	−	−	−	−	−	−	−	−	−	ｘ	ｘ	ｘ	０	０	１	０	０	ｘ	ｘ	imm data

bit data Addition mode options bit17 bit16 bit15 0 0 0 Address addition 0 0 0 1 Address addition 1 0 1 0 Address addition 2 0 1 1 Address addition 4 1 0 0 Address addition 8 1 0 1 Address addition 16 1 1 0 Address addition 32 1 1 1 Address addition 64

bit data choices bit9 bit8 0 0 DATA RAM0 0 1 DATA RAM1 1 0 DATA RAM2 1 1 DATA RAM3

flag

It will be T0;1. **

remarks

* [Mx(x=0~3)] selects DATA RAMx(x=0~3).

** When the END signal indicating the end of transfer from the outside is received, it becomes T0;0.

To specify address addition, add the addition number after the instruction, and specify DMA0 to DMA64.

If address addition number specification is omitted, the addition number will be 1.

DMA D0,[RAM],[s]

DMA transfer (D0[31-0]→RAM)

Operation details

The [s] data specified by bits 0 to 2 is used as the transfer counter, and the indicated number of D0[31-0] data are transferred to the RAM. The external address register and transfer word count register are updated (added) according to the number of address additions. The transfer word count register is a register that stores the number of transfer words in longword units. Transfer ends when this word count becomes 0 or when the transfer is forcibly terminated.

descriptive formula

label: DMA D0,[Destination],[Counter]

Counter = M0~M3 * , MC0~MC3 * ,

Destination = M0~M3 * ,PR *

instruction code

bit15	Addition mode options
0	Address addition 0
1	Address addition 1

31			28													15					10	９	８						２	１	０
１	１	０	０	−	−	−	−	−	−	−	−	−	−	０	０	ｘ	０	１	０	０	ｘ	ｘ	ｘ	−	−	−	−	−	ｘ	ｘ	ｘ

bit data choices bit10 bit9 bit8 0 0 0 DATA RAM0 0 0 1 DATA RAM1 0 1 0 DATA RAM2 0 1 1 DATA RAM3 1 0 0 PROGARM RAM

bit data [s] Choices bit2 bit1 bit0 0 0 0 DATA RAM0 0 0 1 DATA RAM1 0 1 0 DATA RAM2 0 1 1 DATA RAM3 1 0 0 DATA RAM0,CT0++ 1 0 1 DATA RAM1,CT1++ 1 1 0 DATA RAM2,CT2++ 1 1 1 DATA RAM3,CT3++

flag

It will be T0;1. **

CTx(x=0~3);Incremented only when b2=1. There is no change when b2=0.

remarks

* [Mx(x=0~3)] selects DATA RAMx(x=0~3). MCx (x=0~3) selects DATA RAMx (x=0~3) and increments CTx (x=0~3) after transfer.

PR selects PROGRAM RAM.

** When the END signal indicating the end of transfer from the outside is received, it becomes T0;0.

To specify address addition, add the number of additions after the instruction, and specify DMA0 to DMA1.

If address addition number specification is omitted, the addition number will be 1.

DMA [RAM],D0,[s]

DMA transfer (RAM→D0[31-0])

Operation details

The [s] data specified by bits 0 to 2 is used as the transfer counter, and the indicated number of RAM data is transferred to D0[31-0] data. The external address register and transfer word count register are updated (added) according to the number of address additions. However, only addition numbers 0 and 1 are valid for A-Bus, and the writing unit is 32 bits. For B-Bus, all (addition numbers 0-64) are valid. The export unit will be 16 bits, and the 32 bit data will be divided into two and exported at intervals of 16 bits x (0-64). The transfer word count register is a register that stores the number of transfer words in longword units. Transfer ends when this word count becomes 0 or when the transfer is forcibly terminated.

descriptive formula

label: DMA [Source],D0,[Counter]

Counter = M0~M3 * , MC0~MC3 * ,

Source = M0~M3 *

instruction code

bit data Addition mode options bit17 bit16 bit15 0 0 0 Address addition 0 0 0 1 Address addition 1 0 1 0 Address addition 2 0 1 1 Address addition 4 1 0 0 Address addition 8 1 0 1 Address addition 16 1 1 0 Address addition 32 1 1 1 Address addition 64

bit data [s] Choices bit2 bit1 bit0 0 0 0 DATA RAM0 0 0 1 DATA RAM1 0 1 0 DATA RAM2 0 1 1 DATA RAM3 1 0 0 DATA RAM0,CT0++ 1 0 1 DATA RAM1,CT1++ 1 1 0 DATA RAM2,CT2++ 1 1 1 DATA RAM3,CT3++

31			28											17	16	15						９	８						２	１	０
１	１	０	０	−	−	−	−	−	−	−	−	−	−	ｘ	ｘ	ｘ	０	１	１	０	０	ｘ	ｘ	−	−	−	−	−	ｘ	ｘ	ｘ

bit data		[RAM] Choice
bit9	bit8
0	0	DATA RAM0
0	1	DATA RAM1
1	0	DATA RAM2
1	1	DATA RAM3

flag

It will be T0;1. **

CTx(x=0~3);Incremented only when b2=1. There is no change when b2=0.

remarks

* [Mx(x=0~3)] selects DATA RAMx(x=0~3). MCx (x=0~3) selects DATA RAMx (x=0~3) and increments CTx (x=0~3) after transfer.

** When the END signal indicating the end of transfer from the outside is received, it becomes T0;0.

To specify address addition, add the number of additions after the instruction, and specify DMA0 to DMA1.

If address addition number specification is omitted, the addition number will be 1.

DMAH D0,[RAM],SImm

DMA transfer in HOLD state (D0[31-0]→RAM)

Operation details

Transfer D0[31-0] data to RAM. The external address register and transfer word count register retain the value at the start of transfer in the address addition number. The transfer word count register is a register that stores the number of transfer words in longword units. Transfer ends when this word count becomes 0 or when the transfer is forcibly terminated.

descriptive formula

label: DMAH DO,[Destination],Counter

Destination = M0~M3 * ,PR *

instruction code

31			28											17		15					10	９	８	７							０
１	１	０	０	−	−	−	−	−	−	−	−	−	−	０	０	ｘ	１	０	０	０	ｘ	ｘ	ｘ	SImm data

bit15 Addition mode options 0 Address addition 0 1 Address addition 1

bit data choices bit10 bit9 bit8 0 0 0 DATA RAM0 0 0 1 DATA RAM1 0 1 0 DATA RAM2 0 1 1 DATA RAM3 1 0 0 PROGRAM RAM

flag

It will be T0;1. **

remarks

* Mx(x=0~3) selects DATA RAMx(x=0~3).

PR selects PROGRAM RAM.

** When the END signal indicating the end of transfer from the outside is received, it becomes T0;0.

To specify address addition, add the number to add after the instruction, and specify DMAH0 to DMAH1.

If address addition number specification is omitted, the addition number will be 1.

DMAH [RAM],D0,SImm

DMA transfer in HOLD state (RAM→D0[31-0])

Operation details

Transfer RAM data to D0[31-0]. The external address register and transfer word count register retain the value at the start of transfer in the address addition number. The transfer word count register is a register that stores the number of transfer words in longword units. Transfer ends when this word count becomes 0 or when the transfer is forcibly terminated.

descriptive formula

label: DMAH [Source],DO,Counter

Source = M0~M3 *

instruction code

31			28											17	16	15						９	８	７							０
１	１	０	０	−	−	−	−	−	−	−	−	−	−	ｘ	ｘ	ｘ	１	０	１	０	０	ｘ	ｘ	SImm data

bit data Addition mode options bit17 bit16 bit15 0 0 0 Address addition 0 0 0 1 Address addition 1 0 1 0 Address addition 2 0 1 1 Address addition 4 1 0 0 Address addition 8 1 0 1 Address addition 16 1 1 0 Address addition 32 1 1 1 Address addition 64

bit data choices bit9 bit8 0 0 DATA RAM0 0 1 DATA RAM1 1 0 DATA RAM2 1 1 DATA RAM3

flag

It will be T0;1. **

remarks

* Mx(x=0~3) selects DATA RAMx(x=0~3).

** When the END signal indicating the end of transfer from the outside is received, it becomes T0;0.

To specify address addition, add the addition number after the instruction, and specify DMAH0 to DMAH64.

If address addition number specification is omitted, the addition number will be 1.

DMAH D0,[RAM],[s]

DMA transfer in HOLD state (D0[31-0]→RAM)

Operation details

The [s] data specified by bits 0 to 2 is used as the transfer counter, and the indicated number of D0[31-0] data are transferred to the RAM. The external address register and transfer word count register retain the value at the start of transfer in the address addition number. The transfer word count register is a register that stores the number of transfer words in longword units. Transfer ends when this word count becomes 0 or when the transfer is forcibly terminated.

descriptive formula

label: DMAH D0,[Destination],[Counter]

Counter = M0~M3 * ,MC0~MC3 *

Destination = M0~M3 * ,PR *

instruction code

bit15	Addition mode options
0	Address addition 0
1	Address addition 1

31			28													15					10	９	８	７					２	１	０
１	１	０	０	−	−	−	−	−	−	−	−	−	−	０	０	ｘ	１	１	０	０	Ｘ	ｘ	ｘ	−	−	−	−	−	ｘ	ｘ	ｘ

bit data [RAM] Choice bit10 bit9 bit8 0 0 0 DATA RAM0 0 0 1 DATA RAM1 0 1 0 DATA RAM2 0 1 1 DATA RAM3 1 0 0 PROGRAM RAM

bit data [s] Choices bit2 bit1 bit0 0 0 0 DATA RAM0 0 0 1 DATA RAM1 0 1 0 DATA RAM2 0 1 1 DATA RAM3 1 0 0 DATA RAM0,CT0++ 1 0 1 DATA RAM1,CT1++ 1 1 0 DATA RAM2,CT2++ 1 1 1 DATA RAM3,CT3++

flag

It will be T0;1. **

CTx(x=0~3);Incremented only when b2=1. There is no change when b2=0.

remarks

* [Mx(x=0~3)] selects DATA RAMx(x=0~3). MCx (x=0~3) selects DATA RAMx (x=0~3) and increments CTx (x=0~3) after transfer.

** When the END signal indicating the end of transfer from the outside is received, it becomes T0;0.

To specify address addition, add the number of additions after the instruction, and specify DMA0 to DMA1.

If address addition number specification is omitted, the addition number will be 1.

DMAH [RAM],d0,[s]

DMA transfer in HOLD state (RAM→D0[31-0])

Operation details

The [s] data specified by bits 0 to 2 is used as the transfer counter, and the indicated number of RAM data is transferred to D0[31-0] data. The external address register and transfer word count register retain the value at the start of transfer in the address addition number. The transfer word count register is a register that stores the number of transfer words in longword units. Transfer ends when this word count becomes 0 or when the transfer is forcibly terminated.

descriptive formula

label: DMAH [Source],D0,[Counter]

Counter = M0~M3 * ,MC0~MC3 *

Source = M0~M3 *

instruction code

bit data Addition mode options bit17 bit16 bit15 0 0 0 Address addition 0 0 0 1 Address addition 1 0 1 0 Address addition 2 0 1 1 Address addition 4 1 0 0 Address addition 8 1 0 1 Address addition 16 1 1 0 Address addition 32 1 1 1 Address addition 64

bit data [s] Choices bit2 bit1 bit0 0 0 0 DATA RAM0 0 0 1 DATA RAM1 0 1 0 DATA RAM2 0 1 1 DATA RAM3 1 0 0 DATA RAM0,CT0++ 1 0 1 DATA RAM1,CT1++ 1 1 0 DATA RAM2,CT2++ 1 1 1 DATA RAM3,CT3++

31			28											17	16	15						９	８						２	１	０
１	１	０	０	−	−	−	−	−	−	−	−	−	−	ｘ	ｘ	ｘ	１	１	１	０	０	ｘ	ｘ	−	−	−	−	−	ｘ	ｘ	ｘ

bit data		[RAM] Choice
bit9	bit8
0	0	DATA RAM0
0	1	DATA RAM1
1	0	DATA RAM2
1	1	DATA RAM3

flag

It will be T0;1. **

CTx(x=0~3);Incremented only when b2=1. There is no change when b2=0.

remarks

* [Mx(x=0~3)] selects DATA RAMx(x=0~3). MCx (x=0~3) selects DATA RAMx (x=0~3) and increments CTx (x=0~3) after transfer.

** When the END signal indicating the end of transfer from the outside is received, it becomes T0;0.

To specify address addition, add the number of additions after the instruction, and specify DMA0 to DMA1.

If address addition number specification is omitted, the addition number will be 1.