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★ HARDWARE Manual ★ SCSP User's Manual
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SCSP User's Manual/4.1 Register Map
■Slot-specific control register
- The slot-specific control registers represent the register allocation configured for each of the 32 slots (SLOT0 to SLOT31).
- Table 4.1 Address map by slot
slot
SLOT | address | slot
SLOT | address |
|---|
0 | 100000H~100017H | 16 | 100200H~100217H |
1 | 100020H~100037H | 17 | 100220H~100237H |
2 | 100040H~100057H | 18 | 100240H~100257H |
3 | 100060H~100077H | 19 | 100260H~100277H |
4 | 100080H~100097H | 20 | 100280H~100297H |
5 | 1000A0H~1000B7H | 21 | 1002A0H~1002B7H |
6 | 1000C0H~1000D7H | 22 | 1002C0H~1002D7H |
7 | 1000E0H~1000F7H | 23 | 1002E0H~1002F7H |
8 | 100100H~100117H | 24 | 100300H~100317H |
9 | 100120H~100137H | 25 | 100320H~100337H |
10 | 100140H~100157H | 26 | 100340H~100357H |
11 | 100160H~100177H | 27 | 100360H~100377H |
12 | 100180H~100197H | 28 | 100380H~100397H |
13 | 1001A0H~1001B7H | 29 | 1003A0H~1003B7H |
14 | 1001C0H~1001D7H | 30 | 1003C0H~1003D7H |
15 | 1001E0H~1001F7H | 31 | 1003E0H~1003F7H |
- Each register within one slot is described.
- Example of notation method:
- Start address: SA [19:16] indicates that the 4-bit statement from the 16th bit to the 19th bit of SA is allocated.
- Table 4.2 Control registers by slot
| address | MSB | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | LSB |
|---|
| +00h | - | - | - | KX | KB | SBCTL | SSCTL | LPCTL | 8B | SA[19:16] |
|---|
| +02h | SA[15:0] |
|---|
| +04h | LSA[15:0] |
|---|
| +06h | LEA[15:0] |
|---|
| +08h | D2R[4:0] | D1R[4:0] | H.O. | AR[4:0] |
|---|
| +0Ah | - | L.S. | KRS[3:0] | DL[4:0] | RR[4:0] |
|---|
| +0Ch | - | - | - | - | - | - | S.I. | SD | TL[7:0] |
|---|
| +0Eh | MDL[3:0] | MDXSL[5:0] | MDYSL[5:0] |
|---|
| +10h | - | OCT[3:0] | - | FNS[9:0] |
|---|
| +12h | R.E. | LFO[4:0] | PLFOWS | PLFOS[2:0] | ALFOWS | ALFOS[2:0] |
|---|
| +14h | - | - | - | - | - | - | - | - | - | ISEL[3:0] | IMXL[2:0] |
|---|
| +16h | DISDL[2:0] | DIPAN[4:0] | EFSDL[2:0] | EFPAN[4:0] |
|---|
- List 4.1 Slot-specific control registers
- KYONEX(KX) :KEY_ON execution
- KYONB(KB) :KEY_ON,KEY_OFF registration
- SBCTL : Source bit control
- SSCTL : Sound source control
- LPCTL : Loop control
- PCM8B(8B) : Waveform data word length (format) selection
- SA :Start address
- LSA : Loop start address
- LEA : Loop end address
- D2R : Decay 2 rate
- D1R : Decay 1 rate
- EGHOLD(HO) :EG hold mode
- AR :Attack rate
- LPSLNK(LS) :Loop start link
- KRS : Key rate scaling
- DL : Decay level
- RR : release rate
- STWINH(SI) : Stack write protection
- SDIR(SD) :Sound Direct
- TL :Total level
- MDL : Modulation level
- MDXSL : Modulation input X selection
- MDYSL : Modulation input Y selection
- OCT :Octave
- FNS : Frequency number switch
- LFORE(RE) :LFO reset
- LFOF :LFO frequency
- PLFOWS : LFO frequency modulation waveform selection
- PLFOS :LFO frequency modulation depth
- ALFOWS :LFO amplitude modulation waveform selection
- ALFOS :LFO amplitude modulation depth
- ISEL :Input selection
- IMXL : Input mixing level
- DISDL : Direct data transmission level
- DIPAN : Direct data localization
- EFSDL : Effect data transmission level
- EFPAN : Effect data localization
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★ HARDWARE Manual ★ SCSP User's Manual
Copyright SEGA ENTERPRISES, LTD., 1997
