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★ HARDWARE Manual ★ SCSP User's Manual
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SCSP User's Manual/4.1 Register Map
■SCSP control register
- SCSP control registers are allocated to commonly used registers such as interrupt control registers and timer registers.
- Table 4.3 SCSP common control register
| address | MSB | --- | --- | --- | --- | --- | --- | -8- | -7- | --- | --- | --- | --- | --- | --- | LSB |
|---|
| 100400h | - | - | - | - | - | - | M4 | D.B. | VER[7:5] | MVOL[3:0] |
|---|
| 100402h | - | - | - | - | - | - | - | RBL | RBP[7:0] |
|---|
| 100404h | - | - | - | OF | OE | I.O. | IF | - | MIBUF[7:0] |
|---|
| 100406h | - | - | - | - | - | - | - | - | MOBUF[7:0] |
|---|
| 100408h | MSLC[4:0] | CA[3:0] | - | - | - | - | - | - | - |
|---|
| : | Setting prohibited |
|---|
| 100410h | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
|---|
| 100412h | DMEA[15:1] | - |
|---|
| 100414h | DMEA[19:16] | DRGA[11:1] | - |
|---|
| 100416h | - | G.A. | D.I. | EX | DTLG[11:1] | - |
|---|
| 100418h | - | - | - | - | - | TACTL[2:0] | TIMA |
|---|
| 10041Ah | - | - | - | - | - | TBCTL[2:0] | TIMB |
|---|
| 10041Ch | - | - | - | - | - | TCCTL[2:0] | TIMC |
|---|
| 10041Eh | - | - | - | - | - | SCIEB[10:0] |
|---|
| 100420h | - | - | - | - | - | SCIPD[10:0] |
|---|
| 100422h | - | - | - | - | - | SCIRE[10:0] |
|---|
| 100424h | - | - | - | - | - | - | - | - | SCILV0[7:0] |
|---|
| 100426h | - | - | - | - | - | - | - | - | SCILV1[7:0] |
|---|
| 100428h | - | - | - | - | - | - | - | - | SCILV2[7:0] |
|---|
| 10042Ah | - | - | - | - | - | MCIEB[10:0] |
|---|
| 10042Ch | - | - | - | - | - | MCIPD[10:0] |
|---|
| 10042Eh | - | - | - | - | - | MCIRE[10:0] |
|---|
- List 4.2 SCSP common control register
- MEM4MB(M4) : Memory size specification
- DAC18B(DB) : Uses 18-bit D/A converter for digital output
- VER : Version number
- MVOL : Master volume
- RBL : Ring buffer length
- RBP : Ring buffer start address
- MOFULL(OF) : Output FIFO full
- MOEMP(OE) : Output FIFO empty
- MIOVF(IO) : Input FIFO overflow
- MIFULL(IF) :Input FIFO full
- MIBUF : MIDI input data buffer
- MOBUF :MIDI output data buffer
- MSLC : Monitor slot
- CA : call address
- DMEA :DMA transfer start memory address
- DRGA :DMA transfer start register address
- DGATE(GA) : DMA transfer gate 0 clear
- DDIR(DI) :DMA transfer direction
- DEXE(EX) :Start DMA transfer
- DTLG : Number of DMA transfer data
- TACTL : Timer A prescaler control
- TIMA : Timer A count data
- TBCTL : Timer B prescaler control
- TIMB : Timer B count data
- TCCTL : Timer C prescaler control
- TIMC : Timer C count data
- SCIEB :Sound CPU interrupt enable
- SCIPD : Sound CPU interrupt request
- SCIRE : Sound CPU interrupt reset
- SCILV0 : Sound CPU interrupt level bit0
- SCILV1 : Sound CPU interrupt level bit1
- SCILV2 : Sound CPU interrupt level bit2
- MCIEB : Main CPU interrupt enable
- MCIPD : Main CPU interrupt request
- MCIRE : Main CPU interrupt reset
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★ HARDWARE Manual ★ SCSP User's Manual
Copyright SEGA ENTERPRISES, LTD., 1997
