Chapter 1 Overview

■1.1 SCU overview

SCU (System Control Unit) is equipped with CPU I/F, A-Bus I/F, and B-Bus I/F, and smoothly interfaces multiple processors connected via each I/F and bus. It's what you do. Furthermore, it is equipped with a DMA controller, interrupt controller, and DSP.

The DMA controller controls DMA transfer for a total of 4 channels of internal level 2-0 and DSP, and can freely transfer data between the CPU, A-Bus, and B-Bus. Additionally, during DMA execution between A-Bus and B-Bus, the CPU can access the work area using CPU-Bus. However, data transfer requests from the DSP must use the DSP area; for example, for DMA transfers between A-Bus and B-Bus that do not use the DSP area, data transfer requests cannot be made from the DSP. .

The interrupt controller controls all interrupts within the SCU, including interrupts from A-Bus, B-Bus, and SMPC. It also supports timer interrupts and can generate interrupts in synchronization with the screen.

DSP plays the role of accomplishing processing that would be difficult to accomplish on the main CPU due to its overload. The DSP operates at half the operating frequency of the main CPU.
Therefore, 1 step is executed in approximately 70nsec.

◆System configuration diagram

Figure 1.1 shows the system configuration diagram. WORK RAM-H, WORK RAM-L, BACKUP-RAM, IPL ROM, and SMPC are connected to the CPU-Bus, which executes system reset signals and control pad control.

The A-Bus is connected to an external system that supplies software, such as a CD or cartridge. VDP1, VDP2, and SCSP are connected to B-Bus to control video and audio.

Figure 1.1 System configuration diagram

◆Block diagram

Figure 1.2 shows the block diagram of the SCU. As mentioned earlier, the SCU is equipped with a CPU, A-Bus, B-Bus interfaces, DMA controller, interrupt controller, DSP, etc.
Each interface and each controller are connected via a bus to enable data transfer.
The connection between the CPU I/F and A-Bus I/F is made by two buses, the upper one is the connection via the register, and the lower one is the connection used for data transfer. Therefore, DMA transfer is performed using the lower Bus.

Figure 1.2 Block diagram