< 6/31>SCU User's Manual/2.Operation Description

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SCU User's Manual/Chapter 2 Operation Description

◆Specific usage example

●Direct mode

Consider the case of transferring 1KByte from address 2000000H (A-Bus area) to address 6000000H (work RAM) using level 0 DMA. You can perform DMA (direct mode) by following the steps below.

Write the read address (2000000H) to the read address register D0R.
(Loads the read address from the CPU to address 25FE0000H.)
Write the write address (6000000H) to the write address register D0W.
(Loads the write address from the CPU to address 25FE0004H.)
Write the number of transferred bytes (400H) to the transferred byte number register D0C.
(Loads the number of transferred bytes from the CPU to address 25FE0008H.)
Write the address addition value (101H) to the address addition value register D0AD.
(Loads the address addition value from the CPU to address 25FE000CH. Details of the address addition value are described in the address addition value section of this section. In normal DMA, specify 101H as the address addition value.)
Set the DMA mode to 0, set the address update bit and DMA activation factor as necessary, and write to the mode/address update/DMA activation factor register D0MD. For example, if address update is set to hold mode and V-Blank-IN is used as the activation factor, write 0 to D0MD.
(Loads 0 from the CPU to address 25FE0014H.)
When the DMA enable bit is set to 1 and the activation factor set in (5) occurs, DMA is activated and 1KByte data is transferred from address 2000000H (A-Bus area) to address 6000000H (work RAM) at level 0. transfer.
After DMA ends, DMA is activated every time the activation factor set in (5) occurs. At that time, the operation changes depending on the values of the read address update bit (D0RUP) and write address update bit (D0WUP). Figure 2.7 shows the differences in DMA operation depending on the address update bit.

However, (1) to (5) may be in any order. (When the activation factor is set to the DMA activation bit, DMA will be activated each time the DMA operation bit is set to 1 by the CPU.)

Figure 2.7 Differences in DMA operation depending on address update bit

D0RUP=0
When D0WUP=0

D0RUP=0
When D0WUP=1

D0RUP=1
When D0WUP=0

D0RUP=1
When D0WUP=1

When the read address update bit is 0, the same address is referenced (read) both the first and second time. When the read address update bit is 1, the address referenced the second time will refer to the address following the first address.
When the write address update bit is 0, the first and second writes are performed to the same address. When the write address update bit is 1, the second write is performed from the address following the first write.

●Indirect mode

Indirect mode is used when you want to perform multiple DMA transfers with one startup. In indirect mode, instead of setting in a register as in direct mode, DMA is executed by accessing registers via RAM. As an example, consider the case where you want to execute the following three DMA transfers consecutively at level 0 via the work RAM area (6000000H).

(a).20HByte DMA transfer from 4000000H to 5C00000H.
(b).10HByte DMA transfer from 5E00000H to 6080000H.
(c).15HByte DMA transfer from 5A00000H to 6081000H.

You can perform DMA (indirect mode) by following the steps below.

As shown in Figure 2.8, data is written in longword units from the work RAM area (6000000H).

Figure 2.8 Example of data writing

6000000H┏━━━━━━━━━━┓ ┐
        ┃      20H ┃ │ ← (Number of bytes transferred)
        ┠──────────┨ │
        ┃ 5C00000H ┃ │(a)←(Transfer source address)
        ┠──────────┨ │
        ┃ 4000000H ┃ │ ←(Forwarding address)
600000CH┣━━━━━━━━━━┫ ┘
        ┃      10H ┃ │
        ┠──────────┨ │
        ┃ 6080000H ┃ │(b)
        ┠──────────┨ │
        ┃ 5E00000H ┃ │
6000018H┣━━━━━━━━━━┫ ┘
        ┃      15H ┃ │
        ┠──────────┨ │
        ┃ 6081000H ┃ │(c)
        ┠──────────┨ │
        ┃ DA00000H ┃ │ ←8000000H+5A00000H
6000024H┣━━━━━━━━━━┫ ┘ (End code) (Forwarding address)
        ┃          ┃

Write the DMA parameter source address (6000000H) to the write address register (D0W).
Write the address addition value (101H) to the address addition value register D0AD.
(Load the address addition value from the CPU to address 25FE000CH. Details of the address addition value are described in this section in Address addition value. In normal DMA, specify 101H as the address addition value.)
Set the DMA mode to 1, set the address update bit and DMA activation factor as necessary, and write to the mode/address update/DMA activation factor register D0MD. For example, if address update is set to hold mode and V-Blank-IN is used as the activation factor, write 1000000H to D0MD.
(Loads 1000000H from the CPU to address 25FE0014H.)
When the DMA enable bit is set to 1 and the activation factor set in (4) occurs, DMA is activated and DMA transfers (a) to (c) are executed in order until the DMA end code is detected. The DMA end code is a DMA indirect mode end notification code that exists only in the work RAM area, and DMA transfer will continue unless this bit is detected as "1".

However, (1) to (4) may be in any order. In addition, the "read address register (D0R)" and "transfer byte count register (D0C)" that needed to be set in direct mode do not need to be set in indirect mode.
Furthermore, assume that the following DMA transfer is registered in memory.

(d).30HByte DMA transfer from 5000000H to 6090000H.
(e).25HByte DMA transfer from 5100000H to 60A0000H.

At this time, the contents from work RAM area 6000000H are as shown in Figure 2.9.
The DMA is restarted every time the activation factor set in (5) occurs.

Figure 2.9 Contents of work RAM area

6000000H┏━━━━━━━━━━┓
        ┃      20H ┃
        ┠──────────┨
        ┃ 5C00000H ┃
        ┠──────────┨
        ┃ 4000000H ┃
600000CH┣━━━━━━━━━━┫
        ┃      10H ┃
        ┠──────────┨
        ┃ 6080000H ┃
        ┠──────────┨
        ┃ 5E00000H ┃
6000018H┣━━━━━━━━━━┫
        ┃      15H ┃
        ┠──────────┨
        ┃ 6081000H ┃
        ┠──────────┨
        ┃ DA00000H ┃
6000024H┣━━━━━━━━━━┫ ┐
        ┃      30H ┃ │
        ┠──────────┨ │
        ┃ 6090000H ┃ │(d)
        ┠──────────┨ │
        ┃ 5000000H ┃ │
6000030H┣━━━━━━━━━━┫ ┘
        ┃      25H ┃ │
        ┠──────────┨ │
        ┃ 60A0000H ┃ │(e)
        ┠──────────┨ │
        ┃ D100000H ┃ │ ←8000000H+5100000H
600003CH┣━━━━━━━━━━┫ ┘ (End code) (Forwarding address)
        ┃          ┃

When rebooting, the behavior differs depending on whether the DMA mode is retention mode or update mode. Recognition of indirect mode retention/update mode is determined by the write address update bit.

＜ In the case of retention mode (write address update bit = 0)＞

After the first DMA transfer is completed, the address to access the parameter is held at 6000000H, so execute DMA transfers (A) to (C) again.

＜ In case of update mode (write address update bit = 1)＞

After the first DMA transfer is completed, the address for accessing the parameters will be updated to 6000024H, so execute DMA transfers (D) to (E).

●Address addition value

Normally, DMA accesses continuous areas, but by setting an address addition value, it is possible to access addresses at regular intervals. This function is useful when you want to change some of the parameters in a VDP1 command table where the parameters are arranged consecutively. As an example, suppose there are 32 blocks with 20H bytes as one table starting from address 5C00000H. Eventually, we will consider rewriting the parameters in the 8th byte of each block at once. Assuming that there are 40H bytes of parameters to be changed starting from address 6000000H, and when transferring using level 0 DMA, set the following steps and execute the transfer process.

Write read address 6000000H to read address register D0R.
Write write address 5C00008H to write address register D0W.
Write the number of transferred bytes, 40H, to the transferred byte number register D0C.
Write address addition value 105H to address addition value register D0AD.
In this, the lower 3 bits (5=101B) indicate that the address will be updated in 20H increments.
Set the DMA mode to 0, address update bit and DMA activation factor as necessary, and write to the mode/address update/DMA activation factor register D0MD. For example, if address update is set to retention mode and V-Blank-IN is used as the activation factor, write 0 to D0MD.
When the DMA enable bit is set to 1 and the activation factor set in (5) occurs, DMA is activated and the shaded area shown in Figure 2.10 is rewritten at once.

Figure 2.10 Example of DMA transfer execution by setting address addition value

However, (1) to (5) may be in any order.

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