< 7/31>SCU User's Manual/2.Operation Description

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SCU User's Manual/Chapter 2 Operation Description

■2.2 Interrupt control

Table 2.1 shows details of interrupt source bit assignments. The bit assignment represents the interrupt status register. Level 1 is the lowest interrupt level and level F is the highest. A detailed explanation of each interrupt source is given below.

Table 2.1 Interrupt factors
bit allocation Interrupt factor Interrupt source vector number level
bit 0 V-blank-IN VDP2 vector 40 Level F
bit 1 V-blank-OUT VDP2 vector 41 Level E
bit 2 H-blank-IN VDP2 vector 42 level D
bit 3 timer 0 SCU vector 43 level C
bit 4 timer 1 SCU vector 44 Level B
bit 5 DSP-Exit SCU vector 45 Level A
bit 6 Sound-Request SCSP vector 46 level 9
bit 7 SMPC SMPC vector 47 level 8
bit 8 PAD interrupt P.A.D. vector 48 level 8
bit 9 Level-2 DMA finished SCU vector 49 level 6
bit 10 Level-1 DMA ended SCU Vector 4A level 6
bit 11 Level-0 DMA ended SCU Vector 4B level 5
bit 12 DMA-Illegal SCU Vector 4C level 3
bit 13 Sprite drawing finished VDP1 Vector 4D level 2
bit 14 −
bit 15 −
bit 16 external interrupt 00 A-Bus vector 50 level 7
bit 17 External interrupt 01 A-Bus vector 51 level 7
bit 18 External interrupt 02 A-Bus Vector 52 level 7
bit 19 External interrupt 03 A-Bus vector 53 level 7
bit 20 External interrupt 04 A-Bus Vector 54 level 4
bit 21 External interrupt 05 A-Bus vector 55 level 4
bit 22 External interrupt 06 A-Bus vector 56 level 4
bit 23 External interrupt 07 A-Bus vector 57 level 4
bit 24 external interrupt 08 A-Bus Vector 58 level 1
bit 25 external interrupt 09 A-Bus vector 59 level 1
bit 26 external interrupt 10 A-Bus Vector 5A level 1
bit 27 external interrupt 11 A-Bus Vector 5B level 1
bit 28 external interrupt 12 A-Bus Vector 5C level 1
bit 29 external interrupt 13 A-Bus Vector 5D level 1
bit 30 external interrupt 14 A-Bus Vector 5E level 1
bit 31 external interrupt 15 A-Bus Vector 5F level 1

**Table 2.1 Interrupt factors**
bit allocation	Interrupt factor	Interrupt source	vector number	level
bit 0	V-blank-IN	VDP2	vector 40	Level F
bit 1	V-blank-OUT	VDP2	vector 41	Level E
bit 2	H-blank-IN	VDP2	vector 42	level D
bit 3	timer 0	SCU	vector 43	level C
bit 4	timer 1	SCU	vector 44	Level B
bit 5	DSP-Exit	SCU	vector 45	Level A
bit 6	Sound-Request	SCSP	vector 46	level 9
bit 7	SMPC	SMPC	vector 47	level 8
bit 8	PAD interrupt	P.A.D.	vector 48	level 8
bit 9	Level-2 DMA finished	SCU	vector 49	level 6
bit 10	Level-1 DMA ended	SCU	Vector 4A	level 6
bit 11	Level-0 DMA ended	SCU	Vector 4B	level 5
bit 12	DMA-Illegal	SCU	Vector 4C	level 3
bit 13	Sprite drawing finished	VDP1	Vector 4D	level 2
bit 14	−
bit 15	−
bit 16	external interrupt 00	A-Bus	vector 50	level 7
bit 17	External interrupt 01	A-Bus	vector 51	level 7
bit 18	External interrupt 02	A-Bus	Vector 52	level 7
bit 19	External interrupt 03	A-Bus	vector 53	level 7
bit 20	External interrupt 04	A-Bus	Vector 54	level 4
bit 21	External interrupt 05	A-Bus	vector 55	level 4
bit 22	External interrupt 06	A-Bus	vector 56	level 4
bit 23	External interrupt 07	A-Bus	vector 57	level 4
bit 24	external interrupt 08	A-Bus	Vector 58	level 1
bit 25	external interrupt 09	A-Bus	vector 59	level 1
bit 26	external interrupt 10	A-Bus	Vector 5A	level 1
bit 27	external interrupt 11	A-Bus	Vector 5B	level 1
bit 28	external interrupt 12	A-Bus	Vector 5C	level 1
bit 29	external interrupt 13	A-Bus	Vector 5D	level 1
bit 30	external interrupt 14	A-Bus	Vector 5E	level 1
bit 31	external interrupt 15	A-Bus	Vector 5F	level 1

Table 2.2 shows the generic names for interrupt factors. The following explanation will be made using generic terms.

Table 2.2 Generic names of interrupt factors
Interrupt factor generic name Interrupt factor name
blanking interrupt V-blank-IN
V-blank-OUT
H-blank-IN
timer interrupt timer 0
timer 1
DMA end interrupt Level 2-DMA finished
Level 1-DMA finished
Level 0-DMA ended

◆Blanking interrupt

**Table 2.2 Generic names of interrupt factors**
Interrupt factor generic name	Interrupt factor name
blanking interrupt	V-blank-IN
V-blank-OUT
H-blank-IN
timer interrupt	timer 0
timer 1
DMA end interrupt	Level 2-DMA finished
Level 1-DMA finished
Level 0-DMA ended

There are three types of blanking interrupts: V-Blank-IN, V-Blank-OUT, and H-Blank-IN. Figure 2.11 shows details of the blanking interrupt. Blanking interrupts are synchronized with the display and notify the start and end of the display.

Figure 2.11 Blanking interrupt details

●V-Blank-IN

Indicates the end of the display. From now on, if you try to display data on the screen, it will not be displayed on the screen.

●V-Blank-OUT

Represents the start of display. However, even if you notify the start of display, it will take some time (interval) for it to actually be displayed, so take this time into consideration and interrupt the program a little earlier. Also clears timer 0 data.

●H-Blank-IN

Indicates the end of displaying one line. Increment timer 0 data at this timing.

◆Timer interrupt

Timer interrupts include timer 0 and timer 1. The timer interrupt can generate an interrupt at a certain dot (point) on the screen in synchronization with the blanking interrupt described above.

●Timer 0

The value is cleared when the V-Blank-OUT interrupt is received, and counted up when the H-Blank-IN interrupt is received. When compared with the timer 0 compare register (see register details), if the values are the same, a timer 0 interrupt is generated. Figure 2.12 shows the generation process of timer 0.

Figure 2.12 Timer 0 interrupt generation process
(Example when setting compare register = 19)

●Timer 1

Upon reception of the H-blank-IN interrupt, the data in the timer 1 data set register (see register details) is set in timer 1. It counts down at a frequency of approximately 7MHz (1 dot drawing), which is 1/4 of the system clock, and when the value of timer 1 reaches 0, a timer 1 interrupt occurs. Also, depending on the value of the timer 1 mode register (see register details), an interrupt can be generated at one point along with timer 0, or an interrupt can be generated at every line regardless of timer 0. Figure 2.13 shows the process from synchronizing with timer 0 to generating a timer 1 interrupt.

Figure 2.13 Timer 1 interrupt generation process (synchronized with timer 0)

Figure 2.14 shows the process of generating a timer 1 interrupt asynchronously with timer 0. In terms of operation, it is the same as when synchronizing, but each line is judged and an interrupt is generated.

Figure 2.14 Timer 1 interrupt generation process (asynchronous with timer 0)

◆DSP end interrupt

The DSP's ENDI instruction (see Section 4.5, "Instructions" ENDI instruction) sets the program execution control flag (see Section 3.3, E flag of the program control port section) of the program control port (see Section 3.3, Program control port section). is set to notify that the program has finished. This allows the main CPU to retrieve the results calculated by the DSP.

◆Sound-Request interrupt

This is an interrupt generated by SCSP. For example, when a CD (Compact-Disk) is connected, SCSP uses an interrupt to notify the main to display the volume level meter on the screen.

◆SMPC interrupt

For details on interrupts issued by SMPC, please refer to the "SMPC User's Manual".

◆PAD interrupt

This is an interrupt that occurs due to user action. A PAD is used as an example, but other devices such as a mouse may also be connected.

◆DMA end interrupt

Notifies that DMA transfer has finished, depending on the level. There are three levels of DMA, from level 2 to level 0.

◆DMA-Illegal interrupt

When attempting to execute DMA, if it cannot be executed with the parameters, this interrupt will notify that DMA cannot be executed.

◆Sprite drawing end interrupt

VDP1 notifies you that drawing has finished.

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