< 2/19>SMPC User's Manual/1.2 SH-2 Interface

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■1.2 SH-2 interface

◆SH-2 interface register

The SH-2 interface register is a register used for commands from the SH-2, setting command parameters, displaying status, and outputting result parameters.

Figure 1.3 shows the address map of the SH-2 interface register.

Figure 1.3 SH-2 interface register address map

      bit7                0   
         ┌────────────────┐   
2010001FH│     COMREG     │W  
         └────────────────┘   
      bit7                0   
         ┌────────────────┐   
20100061H│      S  R      │R  
         └────────────────┘   
      bit7                0   
         ┌─┬─┬─┬─┬─┬─┬─┬──┐   
20100063H│             │SF│R/W
         └─┴─┴─┴─┴─┴─┴─┴──┘   
      bit7                0   
         ┌────────────────┐┐  
20100001H│     IREG0      ││  
         ├────────────────┤│  
20100003H│     IREG1      ││  
         ├────────────────┤│  
20100005H│     IREG2      ││  
         ├────────────────┤│  
20100007H│     IREG3      │W  
         ├────────────────┤│  
20100009H│     IREG4      ││  
         ├────────────────┤│  
2010000BH│     IREG5      ││  
         ├────────────────┤│  
2010000DH│     IREG6      ││  
         └────────────────┘┘  
      bit7                0            bit7                0
         ┌────────────────┐┐              ┌────────────────┐┐
20100021H│     OREG0      ││     20100041H│     OREG16     ││
         ├────────────────┤│              ├────────────────┤│
20100023H│     OREG1      ││     20100043H│     OREG17     ││
         ├────────────────┤│              ├────────────────┤│
20100025H│     OREG2      ││     20100045H│     OREG18     ││
         ├────────────────┤│              ├────────────────┤│
20100027H│     OREG3      ││     20100047H│     OREG19     ││
         ├────────────────┤│              ├────────────────┤│
20100029H│     OREG4      ││     20100049H│     OREG20     ││
         ├────────────────┤│              ├────────────────┤│
2010002BH│     OREG5      ││     2010004BH│     OREG21     ││
         ├────────────────┤│              ├────────────────┤│
2010002DH│     OREG6      ││     2010004DH│     OREG22     ││
         ├────────────────┤│              ├────────────────┤│
2010002FH│     OREG7      ││     2010004FH│     OREG23     ││
         ├────────────────┤R              ├────────────────┤R
20100031H│     OREG8      ││     20100051H│     OREG24     ││
         ├────────────────┤│              ├────────────────┤│
20100033H│     OREG9      ││     20100053H│     OREG25     ││
         ├────────────────┤│              ├────────────────┤│
20100035H│     OREG10     ││     20100055H│     OREG26     ││
         ├────────────────┤│              ├────────────────┤│
20100037H│     OREG11     ││     20100057H│     OREG27     ││
         ├────────────────┤│              ├────────────────┤│
20100039H│     OREG12     ││     20100059H│     OREG28     ││
         ├────────────────┤│              ├────────────────┤│
2010003BH│     OREG13     ││     2010005BH│     OREG29     ││
         ├────────────────┤│              ├────────────────┤│
2010003DH│     OREG14     ││     2010005DH│     OREG30     ││
         ├────────────────┤│              ├────────────────┤│
2010003FH│     OREG15     ││     2010005FH│     OREG31     ││
         └────────────────┘┘              └────────────────┘┘
         ★Only byte access is possible for all registers

The details of the SH-2 interface registers are shown below.

COMREG(W)：COMmand REGister

This is an 8-bit register for receiving various commands from SH-2. SMPC parses and executes the command as soon as the command is written. SMPC provides reset system management commands, non-reset system management commands, and RTC commands. Please access byte from SH-2.

SR(R)：Status Register

This is an 8-bit register used by SMPC to display the status after command execution. It is possible to read from SH-2 at any time regardless of commands issued. During peripheral control, various statuses of peripheral control are shown. Please access byte from SH-2.

SF(R/W)：Status Flag

Flags for managing command issuance. The SH-2 sets the flag before issuing the command, and the SMPC resets it when the command ends. From SH-2, only set is possible. When setting, please write 01H. When reading, all bits other than bit0 are undefined. This flag can be used to manage duplicate issuance of commands. Please access byte from SH-2.

IREG0~IREG6(W): Input REGister 0~6

This is an 8-bit register for receiving command parameters from SH-2. SMPC has seven IREGs. Please access byte from SH-2.

OREG0~OREG31(R): Output REGister 0~31

This is an 8-bit register for outputting result parameters and peripheral data to SH-2. SMPC has 32 OREGs, which are used to obtain cartridge code, area code, peripheral data, current time, etc. Please access byte from SH-2.

◆Parallel I/O register

This register is used to control the peripheral interface in SMPC. Figure 1.4 shows the parallel I/O register address map. Please note that write-only registers cannot be read.

Figure 1.4 Parallel I/O register address map

*Only byte access is possible for all registers!

DDR1(W)：Data Direction Register 1

This is a 7-bit register that sets the input/output direction of peripheral port 1 (P1) in bit units. Writing "0" to each bit sets it as input, and writing "1" sets it as output. Please access byte from SH-2.

DDR2(W)：Data Direction Register 2

This is a 7-bit register that sets the input/output direction of peripheral port 2 (P2) in bit units. Writing "0" to each bit sets it as input, and writing "1" sets it as output. Please access byte from SH-2.

Table 1.3 DDR function setting values

Setting value	function
0	Set to input (default value)
1	set to output

PDR1(R or W)：Port Data Register 1

PDR1 is a 7-bit register that stores peripheral port 1 (P1) data. Whether each bit of PDR1 is an input port or an output port is determined by the DDR1 settings. By writing data to this register, you can change the pin state of the port set as output. By reading this register, you can read the pin status of the port set as input. Also, for ports set as output, the value written to PDR1 is read, not the pin state. Please access byte from SH-2.

PDR2(R or W)：Port Data Register 2

PDR2 is a 7-bit register that stores peripheral port 2 (P2) data. Whether each bit of PDR2 is an input port or an output port is determined by the DDR2 settings. By writing data to this register, you can change the pin state of the port set as output. By reading this register, you can read the pin status of the port set as input. Also, for ports set as output, the value written to PDR2 is read, not the pin state. Please access byte from SH-2.

IOSEL1(W)：I/O SELect 1

Set peripheral port 1 (P1) to SMPC control mode or SH-2 direct mode. Writing "0" sets SMPC control mode, and writing "1" sets SH-2 direct mode. Please access byte from SH-2.

IOSEL2(W): I/O SELect 2

Set peripheral port 2 (P2) to SMPC control mode or SH-2 direct mode. Writing "0" sets SMPC control mode, and writing "1" sets SH-2 direct mode. Please access byte from SH-2.

Table 1.4 IOSEL functions

Setting value	function
0	Set to SMPC control mode (initial value)
1	Set to SH-2 direct mode

For details on each mode, please refer to Chapter 3 .

Use of SH-2 direct mode is prohibited.
(Excluding peripherals using SH-2 direct mode)

EXLE1(W): EXternal Latch Enable 1

	Use of SH-2 direct mode is prohibited. (Excluding peripherals using SH-2 direct mode)

This bit sets whether to use bit 6 of peripheral port 1 (P1) as a PAD interrupt or VDP2 external latch input. Writing "0" disables it and sets bit 6 of peripheral port 1 as a normal I/O port. Writing "1" enables it, and bit 6 of peripheral port 1 can be used as a PAD interrupt input or an external latch input for VDP2. Please access byte from SH-2.

EXLE2(W): EXternal Latch Enable 2

This bit sets whether to use bit 6 of peripheral port 2 (P2) as a PAD interrupt or VDP2 external latch input. Writing "0" disables it and sets bit 6 of peripheral port 2 as a normal I/O port. Writing "1" enables it, and bit 6 of peripheral port 2 can be used as a PAD interrupt input or an external latch input for VDP2. Please access byte from SH-2.

Table 1.5 EXLE functions

Setting value	function
0	Disabled (default value)
1	enable

EXLE is multiplexed to bit 6 of the I/O port. Therefore, when using EXLE, bit 6 of DDR1/DDR2 must be set to input.

(See VDP2 external latch function and SCU PAD interrupt.)

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