Japanese
★ HARDWARE Manual ★ VDP2 User's Manual ★ Chapter 3 RAM
▲ Back ｜ Forward ▼
VDP2 User's Manual/Chapter 3 RAM/■3.3 How to access VRAM during the display period

●Image data access

In order to display the normal scroll screen (NBG0 to NBG3), the necessary image data must be read from VRAM. The image data required when the display format is cell format is pattern name data and character pattern data, and the image data required when the display format is bitmap format is bitmap pattern data. The number of VRAM accesses required during one cycle to obtain these image data is determined by conditions.

Pattern name data read access during one cycle can only be set to a maximum of two banks: either VRAM-A0 or VRAM-B0, and either VRAM-A1 or VRAM-B1. Do not do it. If VRAM is not divided into two, the register for VRAM-A0 is used for VRAM-A, and the register for VRAM-B0 is used for VRAM-B, so you should not set it for only one of them. not. Access timing can be specified at any timing as long as it is within the register valid range for each TV screen mode. The number of accesses must be specified exactly as determined by the conditions, but it is not necessary to specify them at consecutive times.
Table 3.2 shows the number of pattern name data read accesses, and Figure 3.3 shows the pattern name data read access specification limits.

Table 3.2 Number of accesses to pattern name table data required during one cycle
 item
 NBG0~NBG3
 Reduce settings
 1x
 1/2 times
 1/4 times
 required during one cycle
 VRAM access count
 1
 2
 4

Figure 3.3 Access specification restrictions for pattern name table data

In principle, character pattern data read access during one cycle can be specified at any timing in the four banks. However, the timing that can be specified is limited by the pattern name data access timing. However, only when the pattern name data access of NBG0 and NBG1 is specified as T0, each character pattern data read access can be specified at any timing of the four banks, and there is no restriction. . The number of accesses must be specified exactly as determined by the conditions, but it is not necessary to specify them at consecutive times.
Table 3.3 shows the number of character pattern data read accesses, and Table 3.4 shows the character pattern data read access specification limits.

Table 3.3 Character pattern data (bitmap pattern data) read access count
 item
 NBG0~NBG3
 Number of character colors
 16
 256
 2048
 32768
 16.77 million
 Reduce settings
 1x
 1/2 times
 1/4 times
 1x
 1/2 times
 1x
 1x
 1x
 required during one cycle
 VRAM access count
 1
 2
 4
 2
 4
 4
 4
 8

Table 3.4 Character pattern data read access specification restrictions
 item
 TV screen mode
 character size
 Pattern name table data access timing
 T0
 T1
 T2
 T3
 T4
 T5
 T6
 T7
 character putter
 table data
 Specify access
 timing
 normal
 1 cell horizontal x 1 cell vertical
 2 cells horizontally x 2 cells vertically
 T0〜T2,
 T4～T7
 T0～T3,
 T5～T7
 T0～T3,
 T6～T7
 T0～T3,
 T7
 T0～T3
 T1～T3
 T2, T3
 T3
 High resolution,
 dedicated monitor
 1 cell horizontal x 1 cell vertical
 T0～T2
 T1～T3
 T0,
 T2, T3
 T0, T1,
 T3
 −
 −
 −
 −
 2 cells horizontally x 2 cells vertically
 T0～T2
 T1～T3
 T2, T3
 T3
 −
 −
 −
 −

If the reduction setting is 1x and character pattern data read access is required more than once, you must ensure that all character pattern data read accesses adhere to the specified limit. When the reduction setting is 1/2 times or 1/4 times, the number of accesses required when the reduction setting is 1 times (1 time when the number of character colors is 16 colors, 2 times when the number of character colors is 256 colors) is , the specified limit of one pattern name data read access must be observed. For example, when the number of character colors is 256 and the reduction setting is 1/2, the specification restrictions for character pattern data read access when pattern name data read access is specified as T1 and T3 are as shown in Figure 3.4. Masu.

Figure 3.4 Character pattern data read access specification example

[Note] Character pattern data read access must be specified twice for each specifiable range.

▲ Back ｜ Forward ▼
★ HARDWARE Manual VDP2 User's Manual ★ Chapter 3 RAM
Copyright SEGA ENTERPRISES, LTD., 1997