VDP2 displays scrolling screen data while reading it from VRAM in synchronization with TV scanning. VRAM access during the display period repeats the cycle with 4 or 8 accesses as an operation unit (1 cycle). When the TV screen mode is normal mode, 8 accesses equals 1 cycle. Also, when in high resolution mode or dedicated monitor mode, 4 accesses equals 1 cycle. There are the following 10 types of VRAM accesses performed during one cycle.
- Pattern name data read access on normal scroll screen
- Normal scroll screen character pattern data read access or bitmap pattern data read access
- NBG0, NBG1 vertical cell scroll table data read access
- Read/write access by CPU
- do not access
- RBG0 pattern name data read access
- RBG0 character pattern data read access or bitmap pattern data read access
- RBG0 coefficient table data read access
- RBG1 pattern name data read access
- RBG1 character pattern data read access
For VRAM accesses 1. to 5. above, the timing within one cycle must be specified for each bank of VRAM-A0, VRAM-A1, VRAM-B0, and VRAM-B1. This is specified by writing a 4-bit value called an access command that corresponds to each type of VRAM access to the VRAM cycle pattern register.
VRAM accesses 6. to 8. each occupy the entire timing of one cycle, so only one type can be specified for one bank. The specification is made by writing the value corresponding to each type of VRAM access to the rotation data bank specification bit of the RAM control register. The settings of the VRAM cycle pattern register of the bank specified for VRAM access in 6. to 8. will be invalidated.
The VRAM accesses of 9. and 10. each occupy the entire timing of one cycle, and 9. and 10. are fixed to VRAM-B1 and 10. to VRAM-B0, respectively. 9. and 10. are automatically specified when RBG1 is displayed, and the VRAM cycle pattern register settings for VRAM-B0 and VRAM-B1 are invalidated at that time.
The VRAM cycle pattern register has registers corresponding to each bank of VRAM-A0, VRAM-A1, VRAM-B0, and VRAM-B1. If VRAM is not divided into two, the registers for VRAM-A0 are used for VRAM-A, the registers for VRAM-B0 are used for VRAM-B, and the registers for VRAM-A1 and VRAM-B1 are not used. yeah. The registers corresponding to each bank are divided into eight access timings, T0 to T7, and accesses are performed in order from the VRAM access indicated by the access command specified in the T0 bit. When the TV screen is in normal mode, all T0 to T7 are enabled. In high resolution mode or dedicated monitor mode, only T0 to T3 are valid and T4 to T7 are ignored. Figure 3.2 shows the VRAM cycle pattern register used during one cycle.
Figure 3.2 VRAM cycle pattern register
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Be sure to set "Do not access" any remaining access timing after specifying the VRAM access required for display. Additionally, if the VRAM access address specified in the VRAM cycle pattern register is not an address within the specified bank, access will not occur and correct screen display will not be possible.
