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★ HARDWARE Manual ★ VDP2 User's Manual ★ Chapter 3 RAM
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VDP2 User's Manual/Chapter 3 RAM

■3.2 VRAM bank division

VDP2 allows you to simultaneously access four banks, VRAM-A0, VRAM-A1, VRAM-B0, and VRAM-B1, by dividing VRAM-A and VRAM-B into two. Therefore, it is possible to obtain more image data at once than when not dividing the image into two parts, and it is possible to increase the number of scroll screens that can be displayed at the same time, and to display screens with a large number of colors. However, there are restrictions on specifying VRAM read/write access by the CPU during the display period. Therefore, if you want to perform many read/write accesses by the CPU during the display period, do not divide the VRAM into two, but in normal cases, divide it into two for more efficient access.

●RAM control register

The RAM control register specifies the VRAM bank division, the purpose of VRAM usage for the rotary scroll screen, and the color RAM mode. This is a 16-bit readable and writable register located at address 18000EH. The value is cleared to 0 after power-on or reset, so be sure to set it.

RAMCTL 18000EH
   15   
   14   
   13   
   12   
   11   
   10   
   09   
   08
CRKTE - CRMD1 CRMD0 - - VRBMD VRAMD

   07   
   06   
   05   
   04   
   03   
   02   
   01   
   00
RDBSB11 RDBSB10 RDBSB01 RDBSB00 RDBSA11 RDBSA10 RDBSA01 RDBSA00

Color RAM coefficient table enable bit (CRKTE), bit 15
Please refer to " 6.4 Coefficient table control ".

Color RAM mode bit : Color RAM mode bit (CRMD1, CRMD0), bits 13, 12
Please refer to " 3.4 Color RAM Mode ".

When the CRKTE bit is set to 1, set the color RAM mode to mode 1. At that time, the second half of the color RAM (100800H to 100FFFH) is used for coefficient table data, so color data cannot be stored.

VRAM mode bit : VRAM mode bit (VRBMD, VRAMD)
Controls VRAM bank division.

 VRAMD
 18000EH
 bit 8
 For VRAM-A
 VRBMD
 18000EH
 bit 9
 For VRAM-B

 VRxMD
 process
 0
 Do not split into two banks
 1
 Split into two banks
[Note] A or B is entered for x in the bit name.

Rotation data bank selection bit : RBG0 data bank select bit (RDBSA00 to RDBSB11), bits 7 to 0
Please refer to " 6.2 Rotational scroll screen display control ".
When the CRKTE bit is set to 1, do not specify that the 4 banks of VRAM be used as RAM for coefficient table data.

●Storage location of pattern name data

The pattern name data storage location on the scroll surface has the following restrictions, regardless of whether it is a normal scroll surface or a rotating scroll surface.
Table 3.2 below shows the restrictions on VRAM mode bits and pattern name data storage locations.
Note that there are no restrictions on the storage location of character pattern data or bitmap pattern data.

  1. When neither VRAM-A nor VRAM-B is divided into two
    Can only be stored in either VRAM-A or VRAM-B

  2. When dividing only VRAM-A into two
    a) When storing in VRAM-B, it may be stored in VRAM-A1.
    b) If not stored in VRAM-B, it can be stored in either VRAM-A0 or A1.

  3. When dividing only VRAM-B into two
    a) When storing in VRAM-A, it may be stored in VRAM-B1.
    b) If not stored in VRAM-A, it can be stored in either VRAM-B0 or B1.

  4. When dividing both VRAM-A and VRAM-B into two
    It can only be stored in either VRAM-A0 or VRAM-B0, and either VRAM-A1 or VRAM-B1.

Table 3.2 Limitations on pattern name data storage location
 VRAM mode bit setting value
 Pattern name data storage location
VRAMD VRBMD VRAM-A VRAM-B
VRAM-A0 VRAM-A1 VRAM-B0 VRAM-B1
0 0 ○ ×
× ○
1 0 × ○ ○
○ ○ ×
0 1 ○ × ○
× ○ ○
1 1 ○ ○ × ×
○ × × ○
× ○ ○ ×
× × ○ ○
○: Can be stored
×: Cannot be stored
[Note] If there are multiple locations where it can be stored, it is not necessary to store it in all of them.

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★ HARDWARE Manual VDP2 User's Manual ★ Chapter 3 RAM
Copyright SEGA ENTERPRISES, LTD., 1997