A wait cycle is inserted into the CPU until the end of the write access, but in the case of a write access, no wait cycle is inserted if the write access of two words is made up to two times.
VRAM access by the CPU can only be specified in units of access to VRAM-A or access to VRAM-B, and cannot be specified in units of banks.
When specifying VRAM access by the CPU to a VRAM that is not divided into two, specify the CPU read/write access command in the VRAM cycle pattern register at the timing of the access. At this time, instead of the CPU read/write access command, you can specify an access command that says no access, and the result will be the same. Also, if an access command for a screen that is set not to be displayed (pattern name data read, character pattern data read, or bitmap pattern data read) is set in the screen display enable register, CPU read/write access is Become. For details on the screen display enable register, see 4.1 Screen Display Control .
If you specify an access command for CPU read/write or no access for all access timings of VRAM that is not divided into two, access by the CPU will be possible at any time during the screen display period. Using this, one VRAM can be used as auxiliary work RAM. Also, by switching the VRAM used to display pictures like a frame buffer, you can display pictures while rewriting them at high speed.
For example, when VRAM-A is not divided into two banks, the VRAM cycle pattern register specification when performing CPU read/write access to T2 and T4 is as shown in Figure 3.6.
Figure 3.6 CPU read/write access specification example when VRAM is not divided into two banks
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When setting CPU read/write access to the VRAM that is divided into two, set the CPU read/write access command in the VRAM cycle pattern registers for both bank 0 and bank 1 at the timing of the access. I have to. Furthermore, you must specify an access command that does not access both bank 0 and bank 1 registers at the timing immediately before the CPU read/write access command is set. However, if you want to specify CPU read/write access at consecutive timings, you only need to specify it at the timing immediately before the beginning of the consecutive accesses.
For example, when dividing VRAM-B into two, the VRAM cycle pattern register specification when performing continuous CPU read/write access to T4 and T5 is as shown in Figure 3.7.
Figure 3.7 Example of specifying CPU read/write access when dividing VRAM into two banks
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