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★ HARDWARE Manual ★ VDP2 User's Manual ★ Chapter 3 RAM
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VDP2 User's Manual/Chapter 3 RAM/■3.3 How to access VRAM during the display period
●VRAM cycle pattern register specification procedure
- The procedure for specifying the VRAM cycle pattern to the register is as follows.
- Determines the TV screen mode.
- Decide whether to divide VRAM into two.
- Determine the number of character colors and reduction settings for the scroll screen to be displayed.
Also decide whether to use the vertical cell scrolling feature.
- Determine the VRAM bank to store the image data (pattern name data, character pattern data, bitmap pattern data) required for each scroll screen.
When using the vertical cell scroll function, also determine the VRAM bank that will store the vertical cell scroll table data.
- Decide whether to perform read/write access by the CPU.
- Specify access commands in the VRAM cycle pattern register so as to adhere to the specified restrictions for each access timing.
- Figure 3.8 shows an example of specifying the VRAM cycle pattern register.
- Figure 3.8 VRAM cycle pattern specification example
- ＜ conditions＞
- Set TV screen mode to normal mode
- Split both VRAM-A and VRAM-B
- Set the scroll screen as shown in the table below.
| screen name | Number of character colors | Reduce settings | Vertical cell scrolling function |
|---|
| NBG0 | 256 colors | 1/2 times | do not use |
| NBG1 | 256 colors | 1x | use |
| NBG3 | 16 colors | 1x | - |
- The banks that store each data on the scroll screen should be as shown in the table below.
| screen name | pattern name | charactor
pattern | Vertical cell scroll
table |
|---|
| NBG0 | A0 | B0,B1 | - |
| NBG1 | A0,A1 | B0,B1 | A0 |
| NBG3 | A1 | A1,B0 | - |
- A0: VRAM-A0 A1: VRAM-A1
- B0: VRAM-B0 B1: VRAM-B1
- Enable read/write access to VRAM-A by CPU
- ＜ VRAM cycle pattern register＞
| T0 | T1 | T2 | T3 | T4 | T5 | T6 | T7 |
|---|
For VRAM-A0
(or for VRAM-A) | N1CE | N0PN | N1PN | N0PN | N.A. | CPU | CPU | N.A. |
|---|
For VRAM-A1
| N3CE | N.A. | N1PN | N.A. | N.A. | CPU | CPU | N3CG |
|---|
For VRAM-B0
(or for VRAM-B) | N0CG | N0CG | N1CG | N1CG | N.A. | N0CG | N0CG | N3CG |
|---|
For VRAM-B1
| N0CG | N0CG | N1CG | N1CG | N.A. | N0CG | N0CG | N.A. |
|---|
- N1=NBG1 N2=NBG2 N3=NBG3
- PN=Pattern name data read
- CG=Character pattern data read
- CE=Vertical cell scroll table data read
- CPU=CPU read/write
- NA=Do not access
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★ HARDWARE Manual VDP2 User's Manual ★ Chapter 3 RAM
Copyright SEGA ENTERPRISES, LTD., 1997
