Chapter 4 Scroll screen

■4.1 Screen display control

For scroll screens, you can specify which screens should not be displayed by controlling display VRAM access for each screen. You can also specify for each screen whether to disable the dot color code (transparent code) that is the transparent dot on the displayed screen.

●Screen display enable register

The screen display enable register controls the screen display and transparency code. This is a 16-bit write-only register located at address 180020H. The value is cleared to 0 after power-on or reset, so be sure to set it.

BGON 180020H

15	14	13	12	11	10	09	08
-	-	-	R0TPON	N3TPON	N2TPON	N1TPON	N0TPON

07	06	05	04	03	02	01	00
-	-	R1ON	R0ON	N3ON	N2ON	N1ON	N0ON

　　　　　

Transparent enable bit (N0TPON0, N1TPON, N2TPON, N3TPON, R0TPON)

Specifies whether to disable transparent codes. For the transparent code, see " Transparent dot " in " 4.3 Cell ".

N0TPON	180020H	bit 8	For NBG0 (or for RBG1)
N1TPON	180020H	bit 9	For NBG1 (or for EXBG)
N2TPON	180020H	bit 10	For NBG2
N3TPON	180020H	bit 11	For NBG3
R0TPON	180020H	bit 12	For RBG0

xxTPON	process
0	Enable transparent code (transparent code dots will be transparent)
1	Disable transparent code (transparent code dots are displayed according to their data values)

[Note] xx in the bit name is N0, N1, N2, N3, or R0.

　　　　　　

Screen display enable bit : On bit (N0ON, N1ON, N2ON, N3ON, R0ON, R1ON)

Specify whether to display each scroll screen.

N0ON	180020H	bit 0	For NBG0
N1ON	180020H	bit 1	For NBG1
N2ON	180020H	bit 2	For NBG2
N3ON	180020H	bit 3	For NBG3
R0ON	180020H	bit 4	For RBG0
R1ON	180020H	bit 5	For RBG1

xxON	process
0	Cannot display (does not access VRAM for display)
1	can be displayed

[Note] xx in the bit name can be N0, N1, N2, N3, R0, or R1.

If an access command for a screen with this bit set to 0 is set in the VRAM cycle pattern register, that access command is ignored and no VRAM access is performed to display that screen.
Do not set R1ON to 1 when R0ON is 0.
If both R0ON and R1ON are set to 1, the normal scroll screen cannot be displayed. At this time, VRAM-B0 is fixed to the RAM for the character pattern table of RBG1, and VRAM-B1 is fixed to the RAM for the pattern name table of RBG1.
If a specific screen cannot be displayed due to register settings, set the bit for that screen to 0. For example, if R0ON and R1ON are both set to 1, set the N0ON, N1ON, N2ON, and N3ON bits to 0.
For details on the rotating scroll screen, see " 6.2 Rotating scroll screen display control ."