Chapter 7 Line screen

The line screen has two sides, the line color screen (LNCL) and the back screen (BACK), and you can specify a color for each line or specify a single color for the entire screen. Unlike the scroll screen, characters cannot be displayed. To use a line color screen, data for each line is stored in VRAM as a line color screen table. If it is a single color, the data at the beginning of the table will be used for the entire screen. The line screen is shown in Figure 7.1.

Figure 7.1 Line screen

Line screen table (VRAM)          Line screen
┌──────────────┐      ┏━━━━━━━━━━━━━━───     
│1AAAAAAAAAAAAA│────→ ┃              1st line
├──────────────┤      ┣━━━━━━━━━━━━━━        
│2AAAAAAAAAAAAA│────→ ┃              2nd line
├──────────────┤      ┣━━━━━━━━━━━━━━        
│3AAAAAAAAAAAAA│────→ ┃              3rd line
├──────────────┤      ┣━━━━━━━━━━━━━━        
│4AAAAAAAAAAAAA│      ┃              :       
├──────────────┤      ┃                      
│      :       │      ┃                      
├──────────────┤      ┃                      
                                             
[Note] In the case of single color, the data of the first line is used for the entire screen. 

■7.1 Line color screen

The line color screen (LNCL) is a screen used only for color calculations, and you can choose to specify a single color for the entire screen or specify a color for each line. Stores the color RAM address of the color used in that line in VRAM as line color screen data.

The number of lines specified by one line color screen data changes depending on the interlace setting. In non-interlaced and double-dense interlaced modes, you can specify a color for each line, but in single-dense interlaced mode, you can only specify every two lines.
The line color screen can also be rotated using the line color screen data in the coefficient data. For coefficient data, please refer to " 6.4 Coefficient table control ".
Figure 7.2 shows the structure of the line color screen table for each interlace mode, and Figure 7.3 shows the data structure on the line color screen table.

Figure 7.2 Line color screen table configuration

●Non-interlaced and double-dense interlaced modes

	Bit 15 ← Line color screen table (VRAM) → 0
+00H	1st line color RAM address
+02H	2nd line color RAM address
+04H	3rd line color RAM address
+06H	4th line color RAM address
+08H	5th line color RAM address
+0AH	6th line color RAM address
: :	: :

[note]

In the case of a single color, the color RAM address of the first line is used for the entire line color.
For double-dense interlacing, store line color data for even and odd fields together

●Single dense interlace mode

	Bit 15 ← Line color screen table (VRAM) → 0
+00H	1st and 2nd line color RAM address
+02H	3rd and 4th line color RAM address
+04H	5th and 6th line color RAM address
+06H	7th and 8th line color RAM address
+08H	9th and 10th line color RAM address
+0AH	11th and 12th line color RAM address
: :	: :

[note]

In the case of a single color, the color RAM addresses of the 1st and 2nd lines are used for the entire line color.

Figure 7.3 Bit configuration of line color screen table data

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					Color RAM address 11 bits

part is ignored.

Additionally, when the color RAM mode is mode 0 or mode 2, the most significant bit of the address is ignored.

●Line color screen table address register

The line color screen table address register specifies the color mode of the line color screen and the start address of the table. This is a 32-bit write-only register located at addresses 1800A8H to 1800AAH. The value is cleared to 0 after power-on or reset, so be sure to set it.

LCTAU 1800A8

15	14	13	12	11	10	09	08
LCCLMD	-	-	-	-	-	-	-

07	06	05	04	03	02	01	00
-	-	-	-	-	LCTA18	LCTA17	LCTA16

LCTAL 1800AA

15	14	13	12	11	10	09	08
LCTA15	LCTA14	LCTA13	LCTA12	LCTA11	LCTA10	LCTA9	LCTA8

07	06	05	04	03	02	01	00
LCTA7	LCTA6	LCTA5	LCTA4	LCTA3	LCTA2	LCTA1	LCTA0

　

Line color screen color mode bit : LNCL color mode bit (LCCLMD), bit 15

Specifies the color mode of the line color screen.

LCCLMD	line color screen color
0	Make it monochrome
1	Specify for each line

　

Line color screen table address bit : LNCL table address bit (LCTA18 to LCTA0)

Specify the start address of the line color screen table on VRAM.

LCTA18~LCTA16	1800A8H	bits 2-0
LCTA15~LCTA0	1800AAH	bits 15-0

The actual first VRAM address is calculated using the following formula. If the VRAM capacity is 4Mbits, the most significant bit of the address is ignored.

(Line color screen table start address)
           = (line color screen table address register value 19 bits) x 2H