Japanese
List | Reference
offset: 0C0 | name: (VDP2_TVMD) | Type: ( Uint16 ) |
- Contents: TV screen mode
- reference:
- Register reference: TV screen mode register (TVMD)
List | Reference
offset: 0C2 | name: (VDP2_EXTEN) | Type: ( Uint16 ) |
- Contents: External signal enable
- reference:
- Register reference: External signal enable register (EXREN)
List | Reference
offset: 0C4 | name: (VDP2_TVSTAT) | Type: ( Uint16 ) |
- Contents: Screen status
- reference:
- Register reference: Screen status register (TVSTAT)
List | Reference
offset: 0C6 | name: (VDP2_VRSIZE) | Type: ( Uint16 ) |
- Contents: VRAM size
- reference:
- Register reference: VRAM size register (VRSIZE)
List | Reference
offset: 0C8 | name: (VDP2_HCNT) | Type: ( Uint16 ) |
- Contents: H counter
- reference:
- Register reference: H counter register (HCNT)
List | Reference
offset: 0CA | name: (VDP2_VCNT) | Type: ( Uint16 ) |
- Contents: V counter
- reference:
- Register reference: V counter register (VCNT)
List | Reference
offset: 0CE | name: (VDP2_RAMCTL) | Type: ( Uint16 ) |
- Contents: RAM control
- reference:
- Register reference: RAM control register (RAMCTL)
List | Reference
offset: 0D0 | name: (VDP2_CYCA0L) | Type: ( Uint16 ) |
- Contents: VRAM cycle pattern (bank A0, T0-3)
- reference:
- Register reference: VRAM cycle pattern register (CYCA0L)
List | Reference
offset: 0D2 | name: (VDP2_CYCA0U) | Type: ( Uint16 ) |
- Contents: VRAM cycle pattern (bank A0, T4-7)
- reference:
- Register reference: VRAM cycle pattern register (CYCA0L)
List | Reference
offset: 0D4 | name: (VDP2_CYCA1L) | Type: ( Uint16 ) |
- Contents: VRAM cycle pattern (bank A1, T0-3)
- reference:
- Register reference: VRAM cycle pattern register (CYCA1L)
List | Reference
offset: 0D6 | name: (VDP2_CYCA1U) | Type: ( Uint16 ) |
- Contents: VRAM cycle pattern (bank A1, T4-7)
- reference:
- Register reference: VRAM cycle pattern register (CYCA1U)
List | Reference
offset: 0D8 | name: (VDP2_CYCB0L) | Type: ( Uint16 ) |
- Contents: VRAM cycle pattern (bank B0, T0-3)
- reference:
- Register reference: VRAM cycle pattern register (CYCB0L)
List | Reference
offset: 0DA | name: (VDP2_CYCB0U) | Type: ( Uint16 ) |
- Contents: VRAM cycle pattern (bank B0, T4-7)
- reference:
- Register reference: VRAM cycle pattern register (CYCB0U)
List | Reference
offset: 0DC | name: (VDP2_CYCB1L) | Type: ( Uint16 ) |
- Contents: VRAM cycle pattern (bank B1, T0-3)
- reference:
- Register reference: VRAM cycle pattern register (CYCB1L)
List | Reference
offset: 0DE | name: (VDP2_CYCB1U) | Type: ( Uint16 ) |
- Contents: VRAM cycle pattern (bank B1, T4-7)
- reference:
- Register reference: VRAM cycle pattern register (CYCB1U)
List | Reference
offset: 0E0 | name: (VDP2_BGON) | Type: ( Uint16 ) |
- Contents: Screen display enable
- reference:
- Register reference: Screen display enable register (BGON)
List | Reference
offset: 0E2 | name: (VDP2_MZCTL) | Type: ( Uint16 ) |
- Contents: Mosaic control
- reference:
- Register reference: Mosaic control register (MZCTL)
List | Reference
offset: 0E4 | name: (VDP2_SFSEL) | Type: ( Uint16 ) |
- Contents: Special function code selection
- reference:
- Register reference: Special function code select register (SFSEL)
List | Reference
offset: 0E6 | name: (VDP2_SFCODE) | Type: ( Uint16 ) |
- Contents: Special function code
- reference:
- Register reference: Special function code register (SFCODE)
List | Reference
offset: 0E8 | name: (VDP2_CHCTLA) | Type: ( Uint16 ) |
- Contents: Character control (NBG0, NBG1)
- reference:
- Register reference: Character control register A (CHCTLA)
List | Reference
offset: 0EA | name: (VDP2_CHCTLB) | Type: ( Uint16 ) |
- Contents: Character control (NBG2, NBG3, RBG0)
- reference:
- Register reference: Character control register B (CHCTLB)
List | Reference
offset: 0EC | name: (VDP2_BMPNA) | Type: ( Uint16 ) |
- Contents: Bitmap palette number (NBG0, 1)
- reference:
- Register reference: Bitmap palette number A register (BMPNA)
List | Reference
offset: 0EE | name: (VDP2_BMPNB) | Type: ( Uint16 ) |
- Contents: Bitmap palette number (RBG0)
- reference:
- Register reference: Bitmap palette number B register (BMPNB)
List | Reference
offset: 0F0 | name: (VDP2_PNCN0) | Type: ( Uint16 ) |
- Contents: Pattern name control (NBG0)
- reference:
- Register reference: Pattern name control register NBG0 (PNCN0)
List | Reference
offset: 0F2 | name: (VDP2_PNCN1) | Type: ( Uint16 ) |
- Contents: Pattern name control (NBG1)
- reference:
- Register reference: Pattern name control register NBG1 (PNCN1)
List | Reference
offset: 0F4 | name: (VDP2_PNCN2) | Type: ( Uint16 ) |
- Contents: Pattern name control (NBG2)
- reference:
- Register reference: Pattern name control register NBG2 (PNCN2)
List | Reference
offset: 0F6 | name: (VDP2_PNCN3) | Type: ( Uint16 ) |
- Contents: Pattern name control (NBG3)
- reference:
- Register reference: Pattern name control register NBG3 (PNCN3)
List | Reference
offset: 0F8 | name: (VDP2_PNCR) | Type: ( Uint16 ) |
- Contents: Pattern name control (RBG0)
- reference:
- Register reference: Pattern name control register RBG0 (PNCR)
List | Reference
offset: 0FA | name: (VDP2_PLSZ) | Type: ( Uint16 ) |
- Contents: Plane size
- reference:
- Register reference: Plane size register (PLSZ)
List | Reference
offset: 0FC | name: (VDP2_MPOFN) | Type: ( Uint16 ) |
- Contents: Map offset (NBG0-3)
- reference:
- Register reference: Map offset NBG register (MPOFN)
List | Reference
offset: 0FE | name: (VDP2_MPOFR) | Type: ( Uint16 ) |
- Contents: Map offset (rotation parameters A, B)
- reference:
- Register reference: Map offset RBG register (MPOFR)
return Copyright SEGA ENTERPRISES, LTD., 1997