TVMD     F      87654 210
180000H  ■□□□□□□■■■■■□■■■
         │      │││││ └┴┴── HRESO2,1,0    horizontal resolution
         │      │││└┴────── VRESO1,0      vertical resolution
         │      │└┴──────── LSMD1,0       interlace mode
         │      └────────── BDCLMD        border color mode
         └───────────────── DISP          TV screen display

detail:

■2.4 TV screen mode register

reference:

■1.3 Scroll function

■2.1 TV screen mode

■2.2 Interlace mode

■2.3 TV screen configuration

EXTEN    F     98      10
180002H  □□□□□□■■□□□□□□■■
               ││      │└── EXBGEN        external screen enable
               ││      └─── DASEL         image display area selection
               │└────────── EXSYEN        external synchronization enable 
               └─────────── EXLTEN        external latch enable

detail:

●External signal enable register

reference:

■2.3 TV screen configuration

■2.5 External signals and scanning status

TVSTAT   F     98    3210
180004H  □□□□□□■■□□□□■■■■
               ││    │││└── PAL           TV system flag
               ││    ││└─── ODD           scanning field flag
               ││    │└──── HBLANK        H blank flag
               ││    └───── VBLANK        V blank flag
               │└────────── EXSYFG        external synchronization flag
               └─────────── EXLTFG        external latch flag

detail:

●Screen status register

reference:

■2.3 TV screen configuration

■2.5 External signals and scanning status

VRSIZE   F           3210
180006H  ■□□□□□□□□□□□■■■■
         │           └┴┴┴── VER3..0       version number
         └───────────────── VRAMSZ        VRAM size

detail:

●VRAM size register

reference:

■1.2 Address map

■3.1 Address map

HCNT     F     9876543210
180008H  □□□□□□■■■■■■■■■■
               └┴┴┴┴┴┴┴┴┴── HCT9..0       H counter value

detail:

●H counter register

connection:

●V counter register

reference:

■2.5 External signals and scanning status

VCNT     F     9876543210
18000AH  □□□□□□■■■■■■■■■■
               └┴┴┴┴┴┴┴┴┴── VCT9..0       V counter value

detail:

●V counter register

connection:

●H counter register

reference:

■2.5 External signals and scanning status

         F              0
18000CH  □□□□□□□□□□□□□□□□

	Access prohibited by user! ! !

RAMCTL   F DC  9876543210
18000EH  ■□■■□□■■■■■■■■■■
         │ ││  ││││││││└┴── RDBSA0        rotation data bank specification (for VRAM-A0 or VRAM-A)
         │ ││  ││││││└┴──── RDBSA1        rotating data bank specification (for VRAM-A1)
         │ ││  ││││└┴────── RDBSB0        rotation data bank specification (for VRAM-B0 or VRAM-B)
         │ ││  ││└┴──────── RDBSB1        rotating data bank specification (for VRAM-B1)
         │ ││  │└────────── VRAMD         VRAM mode (for VRAM-A)
         │ ││  └─────────── VRBMD         VRAM mode (for VRAM-A)
         │ └┴────────────── CRMD          color RAM mode
         └───────────────── CRKTE         color RAM coefficient table enable

detail:

●RAM control register

reference:

■1.2 Address map

■3.2 VRAM bank division

■3.4 Color RAM mode

■6.2 Rotational scroll screen display control

■6.4 Coefficient table control

CYCA0L   F              0
180010H  ■■■■■■■■■■■■■■■■
         ││││││││││││└┴┴┴── VCP3A03..0     For timing T3 of VRAM-A3 (or VRAM-A)
         ││││││││└┴┴┴────── VCP2A03..0     For timing T2 of VRAM-A2 (or VRAM-A)
         ││││└┴┴┴────────── VCP1A03..0     For timing T1 of VRAM-A1 (or VRAM-A)
         └┴┴┴────────────── VCP0A03..0     For timing T0 of VRAM-A0 (or VRAM-A)

detail:

●VRAM cycle pattern register

reference:

■3.3 How to access VRAM during the display period

CYCA0U   F              0
180012H  ■■■■■■■■■■■■■■■■
         ││││││││││││└┴┴┴── VCP7A03..0     For timing T7 of VRAM-A3 (or VRAM-A)
         ││││││││└┴┴┴────── VCP6A03..0     For timing T6 of VRAM-A2 (or VRAM-A)
         ││││└┴┴┴────────── VCP5A03..0     For timing T5 of VRAM-A1 (or VRAM-A)
         └┴┴┴────────────── VCP4A03..0     For timing T4 of VRAM-A0 (or VRAM-A)

detail:

●VRAM cycle pattern register

reference:

■3.3 How to access VRAM during the display period

CYCA1L   F              0
180014H  ■■■■■■■■■■■■■■■■
         ││││││││││││└┴┴┴── VCP3A13..0     For timing T3 of VRAM-A1
         ││││││││└┴┴┴────── VCP2A13..0     For timing T2 of VRAM-A1
         ││││└┴┴┴────────── VCP1A13..0     For timing T1 of VRAM-A1
         └┴┴┴────────────── VCP0A13..0     For timing T0 of VRAM-A1

detail:

●VRAM cycle pattern register

reference:

■3.3 How to access VRAM during the display period

CYCA1U   F              0
180016H  ■■■■■■■■■■■■■■■■
         ││││││││││││└┴┴┴── VCP7A13..0     For timing T7 of VRAM-A1
         ││││││││└┴┴┴────── VCP6A13..0     For timing T6 of VRAM-A1
         ││││└┴┴┴────────── VCP5A13..0     For timing T5 of VRAM-A1
         └┴┴┴────────────── VCP4A13..0     For timing T4 of VRAM-A1

detail:

●VRAM cycle pattern register

reference:

■3.3 How to access VRAM during the display period

CYCB0L   F              0
180018H  ■■■■■■■■■■■■■■■■
         ││││││││││││└┴┴┴── VCP3B03..0     For timing T3 of VRAM-B3 (or VRAM-B)
         ││││││││└┴┴┴────── VCP2B03..0     For timing T2 of VRAM-B2 (or VRAM-B)
         ││││└┴┴┴────────── VCP1B03..0     For timing T1 of VRAM-B1 (or VRAM-B)
         └┴┴┴────────────── VCP0B03..0     For timing T0 of VRAM-B0 (or VRAM-B)

detail:

●VRAM cycle pattern register

reference:

■3.3 How to access VRAM during the display period

CYCB0U   F              0
18001AH  ■■■■■■■■■■■■■■■■
         ││││││││││││└┴┴┴── VCP7B03..0     For timing T7 of VRAM-B3 (or VRAM-B)
         ││││││││└┴┴┴────── VCP6B03..0     For timing T6 of VRAM-B2 (or VRAM-B)
         ││││└┴┴┴────────── VCP5B03..0     For timing T5 of VRAM-B1 (or VRAM-B)
         └┴┴┴────────────── VCP4B03..0     For timing T4 of VRAM-B0 (or VRAM-B)

detail:

●VRAM cycle pattern register

reference:

■3.3 How to access VRAM during the display period

CYCB1L   F              0
18001CH  ■■■■■■■■■■■■■■■■
         ││││││││││││└┴┴┴── VCP3B13..0     For timing T3 of VRAM-B1
         ││││││││└┴┴┴────── VCP2B13..0     For timing T2 of VRAM-B1
         ││││└┴┴┴────────── VCP1B13..0     For timing T1 of VRAM-B1
         └┴┴┴────────────── VCP0B13..0     For timing T0 of VRAM-B1

detail:

●VRAM cycle pattern register

reference:

■3.3 How to access VRAM during the display period

CYCB1U   F              0
18001EH  ■■■■■■■■■■■■■■■■
         ││││││││││││└┴┴┴── VCP7B13..0     For VRAM-B1 timing T7
         ││││││││└┴┴┴────── VCP6B13..0     For VRAM-B1 timing T6
         ││││└┴┴┴────────── VCP5B13..0     For VRAM-B1 timing T5
         └┴┴┴────────────── VCP4B13..0     For VRAM-B1 timing T4

detail:

●VRAM cycle pattern register

reference:

■3.3 How to access VRAM during the display period