<26/29>SCSP User's Manual/4.2.12 Interrupt Control

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SCSP User's Manual/4.2 Sound source register

■Interrupt control register

SCSP has a built-in interrupt controller that includes a function to control interrupt signals to the main CPU and a function to control interrupt signals to the sound CPU.

Figure 4.55 Sound interrupt signal connection diagram

The interrupt signal system of the sound block is connected to each CPU around the SCSP interrupt controller. Interrupt signals to the sound CPU are sent using autovector interrupts of levels 1 to 7. For interrupts to the main CPU, level settings and vector settings cannot be made from the sound CPU side.
Interrupts to the main CPU not only function as interrupts, but can also be used as triggers to start DMA transfers in the SCU. This function allows the sound CPU to control the timing of DMA transfer of huge amounts of data such as waveform data. When using this function, be sure to configure the main side (SCU, etc.) in advance so that DMA transfer is started by a sound interrupt. (For details, refer to the SCU user's manual .) please).

The registers are explained below.
There are two parts to interrupts: one that manages interrupts to the main (a register named MC~) and the other that manages interrupts to the sound CPU (a register named SC~).

SCIPD[10:0] ; Sound-Cpu Interrupt PenDing

This is a register (interrupt flag) that monitors interrupts to the sound CPU. When an interrupt request occurs, the corresponding interrupt request flag is set to "1B", so by reading the "SCIPD" register on the CPU, you can find out which interrupt is occurring. In addition, interrupt requests are sequentially monitored regardless of the setting of the interrupt enable register ("SCIEB"). The corresponding flag can be reset by the interrupt reset register ("SCIRE"). Only bit 5 can be read and written; all others are read-only. Writing "1B" to bit 5 causes an interrupt to the sound CPU. However, writing "0B" is invalid.

SCIEB[10:0](R/W) ; Sound-Cpu Interrupt EnaBle

This is the interrupt enable register for the sound CPU. Writing "1B" enables hardware interrupts for the corresponding bit. Whether or not an interrupt has occurred can also be determined by reading "SCIPD" regardless of the "SCIEB" setting. Setting "0B" disables interrupts.

SCIRE[10:0](W) ; Sound-Cpu Interrupt REset

This is the interrupt request reset flag for the sound CPU. Writing "1B" resets the hardware interrupt request of the corresponding bit (by writing "1B" to "SCIRE" corresponding to the bit where an interrupt is generated, " SCIPD" will also change from "1B" to "0B").

MCIPD[10:0](R) ; Main Cpu Interrupty PenDing

This is a register (interrupt flag) that monitors interrupts to the main CPU. When an interrupt request occurs, the corresponding interrupt request flag changes to "1B", so you can know which interrupt is occurring by reading the "MCIPD" register on the CPU. Additionally, interrupt requests are sequentially monitored regardless of the setting of the interrupt enable register ("MCIEB"). The corresponding flag can be reset by the interrupt reset register ("MCIRE"). Only bit 5 can be read and written; all others are read-only. Writing "1B" to bit 5 causes an interrupt to the main CPU. However, writing "0B" is invalid.

MCIEB[10:0](R) ; Main Cpu Interrupty EnaBle

This is the interrupt enable register for the main CPU. Writing "1B" enables hardware interrupts for the corresponding bit. Whether or not an interrupt has occurred can be determined by reading "MCIPD" regardless of the "MCIEB" setting. Setting "0B" disables interrupts.

MCIRE[10:0](R) ; Main CPU Interrupt REset

This is the interrupt request reset flag for the main CPU. Setting "1" resets the hardware interrupt request of the corresponding bit. (also changes from "1B" to "0B").

Figure 4.56 Interrupt register bit correspondence

Table 4.31 Interrupt register bit factors

bit	Interrupt factor
0	Supports interrupt input of external interrupt input "INT0N"
1	Supports interrupt input of external interrupt input "INT1N"
2	Supports interrupt input of external interrupt input "INT2N"
3	Supports MIDI input interrupts An interrupt is generated when data is imported from the empty FIFO buffer memory on the MIDI-IN side. When all data is read from the FIFO buffer and the buffer becomes free, it is automatically released.
4	Supports DMA transfer end interrupt Generates an interrupt when DMA transfer using the built-in SCSP DMA ends (when all data transfer of the block (length (amount)) set in "DLG" is completed).
5	Supports CPU manual interrupts You can interrupt the sound CPU or main by writing to the CPU (main and sound). Writing "1B" causes an interrupt ("0B" is invalid).
6	Supports timer A interrupt
7	Supports timer B interrupt
8	Supports timer C interrupt
9	Supports MIDI output interrupts Generates an interrupt request when the FIFO buffer memory on the MIDI-OUT side is empty. When data is written to the MIDI-OUT buffer memory (register) and it is no longer empty, the interrupt will be automatically canceled.
10	Supports interrupts for each sample (1 sample = 22.68μsec = 1/44.1K time interval).
11～15	invalid

*About SCILV0, 1, and 2

This register sets the autovector interrupt level for the sound CPU. Each register is divided into bits for each interrupt source, so when making settings, you need to look at Figure 4.58 vertically.
Also, the bit 7 column sets the levels of timers B, C, MIDI output interrupts, and interrupts for each sample all at once.
Level settings are performed using a 3-bit code, and each bit is assigned to the SCILV0, 1, and 2 registers.

Figure 4.57 Correspondence between 3-bit code and register

The 3-bit code that sets the level is shown in Figure 4.57. For example, if you set it to 101B, the interrupt level will be 5. "000B" is a level 0 interrupt, so no interrupt is generated.
However, the format of the actual register is as shown in Figure 4.58, so be careful when making settings.

Figure 4.58 Interrupt level setting register format

SCILV0[7:0](W) ; Sound-Cpu Interrupt LeVel bit0

Specifies bit 0 of the interrupt level code for the sound CPU defined by bit correspondence.

SCILV1[7:0](W) ; Sound-Cpu Interrupt LeVel bit1

Specifies bit 1 of the interrupt level code for the sound CPU defined by bit correspondence.

SCILV2[7:0](W) ; Sound-Cpu Interrupt LeVel bit2

Specify bit 2 of the interrupt level code for the sound CPU defined by bit correspondence.

An example of interrupt settings is shown below.

Interrupt setting example

Condition: When interrupting the main CPU with an interrupt from timer A, and issuing a level 6 interrupt to the sound CPU

Procedure: Assuming that no interrupts are currently occurring, complete all interrupt settings and then set the timer.

1 : Set the sound CPU interrupt level to 6.

Level 6 is "110B" in 3-bit code. Also, the bit that manages timer A interrupts is bit 6, so

"0B" in bit 6 of "SCILV0"

("00H" in byte at address 100425H, or "0000H" in word at address 100424H)

"1B" in bit 6 of "SCILV0"

("40H" in byte at address 100427H or "0040H" in word at address 100426H)

"1B" in bit 6 of "SCILV0"

("40H" in byte at address 100429H or "0040H" in word at address 100428H)

Set. This completes the interrupt level setting.

2 : Set parameters in the "MCIEB" and "SCIEB" registers so that interrupts are applied to the main and sound CPUs.
So that timer A interrupts the main CPU,

Write "1B" to bit 6 of the "MCIEB" register .

("40H" in byte at address 10042BH or "0040H" in word at address 10042AH)

Also, the sound CPU will also receive an interrupt,

Write "1B" to bit 6 of "SCIEB" .

("40H" in byte at address 100421FH or "0040H" in word at address 10041EH)

Furthermore, by setting parameters to the timer, it will start counting immediately after that, and an interrupt will be generated if an overflow occurs.

3 : To release interrupts, use the main and sound CPU reset registers.

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