< 3/31>SCU User's Manual/1.3 SCU Register Map

▲ Back ｜ Forward ▼

SCU User's Manual/Chapter 1 Overview

■1.3 SCU register map

Figure 1.6 shows the SCU register map. The SCU register is assigned to the highest address in the SCU mapping area, and a 208-byte area is reserved as shown in Figure 1.3. Also, the map of each register area is shown below.

**Figure 1.6 SCU register map**
25FE0000H	Level-0 DMA set register	32bytes
25FE0020H	Level-1 DMA set register	32bytes
25FE0040H	Level-2 DMA set register	32bytes
25FE0060H	unused	16byte
25FE0070H	unused	16byte
25FE0080H	DSP program control port	4bytes
25FE0084H	DSP program RAM data port	4bytes
25FE0088H	DSP data RAM address port	4bytes
25FE008CH	DSP data RAM data port	4bytes
25FE0090H	Timer 0 compare register	4bytes
25FE0094H	Timer 1 set data register	4bytes
25FE0098H	Timer 1 mode register	4bytes
25FE009CH	unused	4bytes
25FE00A0H	interrupt mask register	4bytes
25FE00A4H	Interrupt status register	4bytes
25FE00A8H	A-Bus interrupt acknowledge	4bytes
25FE00ACH	unused	4bytes
25FE00B0H	A-Bus setting register	8byte
25FE00B8H	A-Bus refresh register	4bytes
25FE00BCH	unused	8byte
25FE00C4H	SCU SDRAM selection register	4bytes
25FE00C8H	SCU version register	4bytes
25FE00CCH	unused	4bytes

Note
- Access (read/write) to unused areas is prohibited.
・ Be sure to use the cache-through address to access the SCU register.

◆Level 2-0 DMA set register

Note	- Access (read/write) to unused areas is prohibited. ・ Be sure to use the cache-through address to access the SCU register.

Figure 1.7 shows the level 2-0 DMA set register map. This register contains parameters required for DMA transfers. As shown in the SCU register map (Figure 1.6), there are three types of DMA levels (level 0 to level 2), so the addresses in Figure 1.7 are expressed as relative addresses.

Figure 1.7 Level 2-0 DMA Set Register Map

bit
31

24

23

16

15

8

7

0

+00H − Read address (in bytes) (R/W)

+04H − Write address (in bytes) (R/W)

+08H Write address (in bytes) (R)

+0CH − 1 − 2

+10H − 3 − 4

+14H − 5 − 6 − 7 − 8

+18H −

+1CH −

In the diagram

Read address addition value Export address addition value DMA enable bit (=0:Disable/=1:Enable) DMA activation bit DMA mode bit Read address update bit (=0: Retain/=1: Update Write address update bit (=0: Retain/=1: Update) DMA activation factor selection bit

◆DSP program control port

Figure 1.10 shows a map of the DSP program control ports. DSP control register. It also stores the DSP operation start address and end address.

Figure 1.10 DSP program control port map

bit	31					26		24	23							16	15								7							０
25FE0080H	−					1	2	−	3	4	5	6	7	8	9	10	11	−							Program RAM address

In the diagram

Cancellation of pause when EX=1 (=0: Not executed/=1: Executed) Pause execution when EX=1 (=0: not executed/=1: executed) D0 bus use DMA transfer execution flag sign flag zero flag carry flag overflow flag Program end interrupt flag Program step execution control bit (=0: Not executed/=1: Executed Program execution control (=0:/=1:) Program counter load permission (=0: not executed/=1: executed)

◆DSP program RAM data port

Figure 1.11 shows a map of the DSP program RAM data ports. Used as an intermediary when transferring program data from the CPU to the DSP.

Figure 1.11 DSP program RAM data port map E>

bit
31
　
　
　
　
26
　
24

23
　
　
　
　
　
　
16

15
　
　
　
　
　
　
　

7
　
　
　
　
　
　
０

7
0

25FE0084H Program RAM data (W)

◆DSP data RAM address port

Figure 1.12 shows the DSP data RAM address port map. Specify the data RAM address when accessing the data RAM inside the DSP from the CPU.

Figure 1.12 DSP data RAM address port map

bit
31
　
　
　
　
26
　
24

23
　
　
　
　
　
　
16

15
　
　
　
　
　
　
　

7
　
　
　
　
　
　
０

25FE0088H − data RAM
address

◆DSP data RAM data port

Figure 1.13 shows a map of the DSP data RAM data ports. DSP data RAM The contents of the address indicated by the address port are stored. When written from the CPU, the data is stored in the DSP's data RAM, and when read from the CPU, the data in the DSP's internal RAM can be retrieved.

Figure 1.13 DSP data RAM data port map
bit
31
　
　
　
　
26
　
24

23
　
　
　
　
　
　
16

15
　
　
　
　
　
　
　

7
　
　
　
　
　
　
０

25FE008CH Data RAM data (W)

◆Timer 0 compare register

Figure 1.14 shows the timer 0 compare register map. Timer 0 generates an interrupt in synchronization with the V-Blank-IN interrupt (see Section 2.2, Interrupt Control). Operation is explained in Section 2.2, and register contents are explained in Chapter 3.

Figure 1.14 Timer 0 compare register map
bit
31
　
　
　
　
　
　
　

　
　
　
　
　
　
　
　

　
　
　
　
　
　
９
　

　
　
　
　
　
　
　
０

25FE0090H − counter value

◆Timer 1 set data register

Figure 1.15 shows the timer 1 set data register map. Timer 1 is set with data by the H-Blank-IN interrupt (see Section 2.2, Interrupt Control), is decremented at a 7MHz cycle, and when the data becomes 0, an interrupt is generated. Operation is explained in Section 2.2, and register contents are explained in Chapter 3.

Figure 1.15 Timer 1 set data register map
bit
31
　
　
　
　
　
　
　

　
　
　
　
　
　
　
　

　
　
　
　
　
　
　
８

　
　
　
　
　
　
　
０

25FE0094H − set data

◆Timer 1 mode register

Figure 1.16 shows the timer 1 mode register map. This register specifies at what timing Timer 1 is generated. Operation is explained in Section 2.2, and register contents are explained in Chapter 3.

Figure 1.16 Timer 1 mode register map
bit
31
　
　
　
　
　
　
　

　
　
　
　
　
　
　
　

　
　
　
　
　
　
　
８

　
　
　
　
　
　
　
０

25FE0098H − 1 − 2

In the figure,

1.Timer 1 mode bit

=0: Occurs every line

=1: Occurs only on the line specified by timer 0

2.Timer operation enable bit

=0: Timer operation OFF

=1: Timer operation ON

◆Interrupt mask register

Figure 1.17 shows the interrupt mask register map. When this bit is 0, interrupts are not masked and interrupts are generated according to requests. Also, when set to 1, interrupts are masked, so no interrupts occur. The details of bit0 (number 15 in the figure) to bit13 (number 2 in the figure) will be explained in detail in Chapter 3.

Figure 1.17 Interrupt mask register map
bit
31
　
　
　
　
　
　
　

　
　
　
　
　
　
　
　

15
　
　
　
　
　
　
　

　
　
　
　
　
　
　
０

25FE00A0H − 1 − 2 3 4 5 6 7 8 9 10 11 12 13 14 15

In the figure,

1.A-Bus interrupt bit

2~15.Interrupt mask bits

◆Interrupt status register

Figure 1.18 shows the interrupt status register map. This register is a readable and writable register, and when read, if the bit data is 0, it means that no interrupt has occurred, and if it is 1, it means that an interrupt has occurred. When writing, writing 0 resets the interrupt, writing 1 retains the current interrupt state. More information about this register is provided in Chapter 3.

Figure 1.18 Interrupt status register map
bit
31
　
　
　
　
　
　
24

23
　
　
　
　
　
　
16

15
　
　
　
　
　
　
8

7
　
　
　
　
　
　
0

25FE00A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 − 17 18 19 20 21 22 23 24 25 26 27 28 29 30

In the figure,

1 to 30. Interrupt status bits

◆A-Bus interrupt acknowledge register

Figure 1.19 shows the A-Bus interrupt acknowledge map. This bit is a readable/writable bit, and has different meanings when reading and writing. Details are explained in Chapter 3.

Figure 1.19 A-Bus interrupt acknowledge register map
bit
31
　
　
　
　
　
　
　

　
　
　
　
　
　
　
　

　
　
　
　
　
　
　
　

　
　
　
　
　
　
　
０

25FE00A8H − 1

In the figure,

1.READ: A-Bus interrupt acknowledge enable bit (=0: Disabled/=1: Enabled)

WRITE: A-Bus interrupt acknowledge enable bit (=0: Disabled/=1: Enabled)

◆A-Bus setting register

Figure 1.20 shows the A-Bus configuration register map. Each of the look-ahead enable bit, precharge insertion bit, and external wait enable bit is disabled when it is 0 and enabled when it is 1. Details are explained in Chapter 3.

Figure 1.20 A-Bus configuration register map

bit
31
　
　
　
　
　
　
24

23
　
　
　
　
　
　
16

15
　
　
　
　
　
　
8

7
　
　
　
　
　
　
0

25FE00B0 − ２３４５６７８９ 10 11 12 13 14 − 15 − 17 18 19 20 21 22 23 24 25 26 27 28 29 − 30

25FE00B4 − 32 33 34 − − − − − − − − 35 36 − 37 38 39 40 41 42 43 44 45 46 47 − 49 50 51 − 52

In the diagram

    2. CS0 space, precharge insertion bit after write　
    3. CS0 space, precharge insertion bit after read　
    4. CS0 space, external weight valid bit　
  5~8. CS0 space, burst cycle wait number setting bit　
 9~12. CS0 space, normal cycle wait number setting bits　
13~14. CS0 space, burst length setting bit　
   15. CS0 space, bus size setting bit　

   17. CS1 space, precharge insertion bit after write　
   18. CS1 space, precharge insertion bit after read　
   19. CS1 space, external weight valid bit　
20~23. CS1 space, burst cycle wait number setting bit　
24~27. CS1 space, normal cycle wait number setting bit　
28~29. CS1 space, burst length setting bit　
   30. CS1 space, bus size setting bit　

   32. CS2 space, precharge insertion bit after write　
   33. CS2 space, precharge insertion bit after read　
   34. CS2 space, external weight valid bit　
35~36. CS2 space, burst length setting bit　
   37. CS2 space, bus size setting bit　

   39. Spare space, precharge insertion bit after writing　
   40. Reserve space, precharge insertion bit after read　
   41. Reserve space, external weight valid bit　
42~45. Reserve space, burst cycle wait number setting bits　
46~49. Spare space, normal cycle wait number setting bits　
50~51. Spare space, burst length setting bit　
   52. Reserve space, bus size setting bit

◆A-Bus refresh register

Figure 1.21 shows the A-Bus refresh register map. Configure settings for A-Bus refresh.

Figure 1.21 A-Bus refresh register map

bit
31
　
　
　
　
　
　
　

　
　
　
　
　
　
　
　

　
　
　
　
　
　
　
　

　
　
　
４
　
　
　
０

25FE00B8H − 1 2 3 4 5

In the figure,

1.A-Bus refresh output enable bit (=0: Disabled/=1: Enabled)

2~5.A-Bus refresh wait number setting bit

◆SCU SDRAM selection register

Figure 1.22 shows the SCU SDRAM selection register map.

Figure 1.22 SCU SDRAM selection register map
bit
31
　
　
　
　
　
　
　

　
　
　
　
　
　
　
　

　
　
　
　
　
　
　
　

　
　
　
　
　
　
　
０

25FE00C4H − 1

In the figure,

1.SDRAM selection bit

◆SCU version register

Figure 1.23 shows the SCU version register map.

Figure 1.23 SCU version register map

bit
31
　
　
　
　
　
　
　

　
　
　
　
　
　
　
　

　
　
　
　
　
　
　
　

　
　
　
　
３
　
　
０

25FE00C8H − 1 2 3 4

In the figure,

1~4.Version number

▲ Back ｜ Forward ▼

★ HARDWARE Manual ★ SCU User's Manual

bit	31		24	23	16	15	8	7		0
+00H	−	Read address (in bytes) (R/W)
+04H	−	Write address (in bytes) (R/W)
+08H	Write address (in bytes) (R)
+0CH	−						1	−	2
+10H	−						3	−		4
+14H	−		5	−	6	−	7	−	8
+18H	−
+1CH	−

bit	31	26	24	23	16	15	7	０
	7		0
25FE0084H	Program RAM data (W)

bit	31					26		24	23							16	15								7							０
25FE0088H	−																								data RAM address

bit	31					26		24	23							16	15								7							０
25FE008CH	Data RAM data (W)

bit	31																						９									０
25FE0090H	−																						counter value

bit	31																							８								０
25FE0094H	−																							set data

bit	31							24	23							16	15							8	7							0
25FE00A4	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	−		17	18	19	20	21	22	23	24	25	26	27	28	29	30

bit	31							24	23							16	15							8	7							0
25FE00B0	−	２	３	４	５	６	７	８	９	10	11	12	13	14	−	15	−	17	18	19	20	21	22	23	24	25	26	27	28	29	−	30
25FE00B4	−	32	33	34	−	−	−	−	−	−	−	−	35	36	−	37	38	39	40	41	42	43	44	45	46	47	−	49	50	51	−	52