Figure 2.1 shows the basic operation of DMA. This DMA basically uses longword access via the DMA controller's buffer, but if the start address or end address is not on a longword boundary, the DMA transfer can be performed by reading or writing byte by byte. I can.
Figure 2.1 is an example of executing DMA transfer from transfer source address 1H to 50H to transfer destination address 6H to 55H. At the transfer source, the longword boundary is 4H, so 1H to 3H are read in bytes. Masu. On the other hand, at the transfer destination, the longword boundary is 8H, so the first 2 bytes of the read data are written to 6H to 7H in bytes. Furthermore, the transfer source end address is 50H, but the longword boundary is up to 4FH, so the data at 50H is read in bytes. On the other hand, the transfer destination end address is 55H, but the longword boundary is up to 53H, so the last 2 bytes read are written in bytes from 54H to 55H.
Figure 2.1 Basic DMA transfer operation
There are two startup methods for SCU DMA transfer control.
DMA start from main CPU DMA activation from DSP
Figure 2.2 shows the DMA transferable area when activated from the main CPU, and Figure 2.3 shows the DMA transferable area when activated from the DSP.
Figure 2.2 DMA transferable area when started from the main CPU
Figure 2.3 DMA transferable area when activated from DSP
Notes on DMA
●Prohibition of writing to A-Bus by SCU-DMA
SCU-DMA writes to A-Bus cannot be used.
●Prohibition of writing by SCU-DMA from VDP2 area
Writing by SCU-DMA from the VDP2 area cannot be used.
●SCU-DMA cannot be used for WORKRAM-L
Only WORKRAM-HI (SDRAM: 1Mbyte) can be used with SCU-DMA in WORKRRAM.
●Prohibition of access to A-Bub and B-Bus from the CPU during A-Bus←→B-Bus DMA operation
During DMA operation from A-Bus to B-Bus or from B-Bus to A-Bus, access to A-Bus and B-Bus from the CPU is prohibited. This is because refresh may no longer occur to SDRAM during wait, resulting in a hang.
●Waiting for SCU-DMA startup of A-Bus←→B-Bus when writing to A-Bus and B-Bus by CPU
Write processing by the CPU to A-Bus and B-Bus has priority over SCU-DMA activation of A-Bus and B-Bus.
For example, when the CPU is executing continuous write to VDP1 (B-Bus), if you start SCU-DMA from A-Bus to VDP2 (B-Bus), the continuous write will end. SCU-DMA will not be started until
However, while SCU-DMA is running, CPU access to A-Bus and B-Bus is put on hold.
●The number of channels that can be used simultaneously with DMA is 2.
The number of channels that can be used simultaneously with guaranteed DMA priority is up to 2 channels.
If three channels are used at the same time, the priority order will be ignored. (DSP DMA command is also counted as one channel)
●Starting DMA level 2 is prohibited while DMA level 1 is running.
If DMA level 2 is activated while DMA is activated at level 1, malfunction may occur.
As a countermeasure, please do not start DMA level 2 while starting at DMA level 1.
●Prohibit writing at the corresponding level while DMA is running
The contents of the DMA mode, address update, activation factor selection register, and addition value register must not be rewritten while the DMA is activated at that level.
If you rewrite it, it will hang.
●Prohibitions of SCU-DMA indirect mode
Disables the use of SCU-DMA indirect mode for reading from the CD buffer.
Please use SCU-DMA direct mode, CPU-DMA or software to transfer.
For transfers using the A-BUS space as the source in addition to the CD buffer, only "4-byte addition" can be specified for the source read address addition value , and "no addition" cannot be set.
This restriction does not apply to SCU-DMA direct mode.
