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★ HARDWARE Manual ★ SCU User's Manual ★ 3.1 Register List
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SCU User's Manual/Chapter 3 Register details

■3.2 DMA control register

The DMA control register consists of the following registers.

◆Level 2-0 DMA set register

There are three DMA levels, from level 2, which has the highest priority, to level 0, which has the lowest priority.

●Reading address
Figure 3.1 shows the details of the read address register. There are two DMA modes: direct mode and indirect mode, and the meaning of the value changes depending on each mode.

Figure 3.1 Level 2-0 read address (registers: D0R, D1R, D2R) Initial value undefined
bit 
31
  
  
  
  
  
  
24
 
23
  
  
  
  
  
  
16
 
15
  
  
  
  
  
  
8 
7 
  
  
  
  
  
  
0 
25FE0000 (level 0)
25FE0020(Level 1)
25FE0040 (Level 2)
 − − − − − １ ２ ３ ４ ５ ６ ７ ８ ９ 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Read address ( 1 to 27 [bit 26 to 0] in Figure 3.1 )
DxR26-0[x=2-0](R/W) DMA level 2-0 Read address bit26-0
In direct mode, the stored value is the transfer source address. On the other hand, when it is in indirect mode, it has no meaning. While DMA is operating, registers at that level are write-protected. All address values are expressed in bytes.

●Export address
Figure 3.2 shows details of the write address register. There are two DMA modes: direct mode and indirect mode, and the meaning of the value changes depending on each mode.

Figure 3.2 Level 2-0 write address (registers: D0W, D1W, D2W) Initial value undefined
bit 
31
  
  
  
  
  
  
24
 
23
  
  
  
  
  
  
16
 
15
  
  
  
  
  
  
8 
7 
  
  
  
  
  
  
0 
25FE0004 (Level 0)
25FE0024 (Level 1)
25FE0044 (Level 2)
 − − − − − １ ２ ３ ４ ５ ６ ７ ８ ９ 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Export address ( 1 to 27 [bit 26 to 0] in Figure 3.2 )
DxW26-0[x=2-0](R/W) DMA level 2-0 Write address bit26-0
In direct mode, the stored value is the transfer destination address. On the other hand, in indirect mode, the address containing the transfer source address of the first DMA transfer is stored. While DMA is operating, registers at that level are write-protected. All address values are expressed in bytes.

●Number of bytes transferred
Stores the number of bytes transferred by DMA. Figure 3.3 shows the details of the number of bytes transferred at level 0, and Figure 3.4 shows the details of the number of bytes transferred at level 2-1.

Figure 3.3 Number of level 0 transfer bytes (register: D0C) Initial value undefined
bit 
31
  
  
  
  
  
  
24
 
23
  
  
  
  
  
  
16
 
15
  
  
  
  
  
  
8 
7 
  
  
  
  
  
  
0 
 25FE0008 (Level 0)
 − − − − − − − − − − − − １ ２ ３ ４ ５ ６ ７ ８ ９ 10 11 12 13 14 15 16 17 18 19 20

Level 0 transfer byte count ( 1 to 20 [bit 19 to 0] in Figure 3.3 )
D0C19-0(W) DMA level 0 Count bit19-0
Stores the number of bytes for DMA transfers operating at level 0. While DMA is operating, registers at that level are write-protected. This register can be set up to 1MByte.

Figure 3.4 Level 2-1 transfer byte count (register: D1C, D2C) initial value undefined
bit 
31
  
  
  
  
  
  
24
 
23
  
  
  
  
  
  
16
 
15
  
  
  
  
  
  
8 
7 
  
  
  
  
  
  
0 
25FE0028 (Level 1)
25FE0048 (Level 2)
 − − − − − − − − − − − − − − − − − − − − １ ２ ３ ４ ５ ６ ７ ８ ９ 10 11 12

Level 2-1 transfer byte count ( 1 to 12 [bit 11 to 0] in Figure 3.4 )
DxC11-0[x=2-1](W) DMA level 2-1 Count bit11-0
Stores the number of bytes for DMA transfers operating at level 2 or 1. While DMA is operating, registers at that level are write-protected. This register can be set up to 4KByte.

Disable reading of number of transferred bytes in DMA transfer register

The read value of the number of transferred bytes in the DMA transfer register is not guaranteed. This register cannot be read. This is a write-only register.

■Operation when the number of DMA transfer bytes is set to '0'
When the number of transfer bytes of SCU-DMA is set to '0', the number of transfers will be the maximum value for each setting.

detail:
Developer's Information Supplement regarding the number of transferred bytes of STN-39/SCU-DMA

●Addition value register
Figure 3.5 shows details of the addition value register.

Figure 3.5 Level 2-0 address addition value (register: D0AD, D1AD, D2AD) initial value 00000101H
bit 
31
  
  
  
  
  
  
24
 
23
  
  
  
  
  
  
16
 
15
  
  
  
  
  
  
8 
7 
  
  
  
  
  
  
0 
25FE000C (Level 0)
25FE002C (Level 1)
25FE004C (Level 2)
 − − − − − − − − − − − − − − − − − − − − − − − １ − − − − − ２ ３ ４

Read address addition value ( 1 [bit 8] in Figure 3.5 )
DxRA[x=2-0](W) DMA level 2-0 Read address Addition data bit
Specify the number of bytes to add to the read address. Table 3.2 shows the read address addition values. This is valid only for the A-Bus CS2 space, otherwise set it to 1B. While DMA is operating, registers at that level are write-protected.

Table 3.2 Read address addition value 
 DxRA(x=2−0)
 Contents
 0
 Not added.
 1
 Add 4Bytes.

Write address addition value ( 2 to 4 [bits 2 to 0] in Figure 3.5 )
DxWA3-0[x=2-0](W) DMA level 2-0 Write address Addition data bit3-0
Specify the number of bytes to add to the write address. Table 3.3 shows the write address addition values. All of this is valid when writing to B-Bus, but only data 000B or 010B can be set when writing to A-Bus CS2 space. When writing to a bus other than A-Bus or B-Bus, set the data to 010B. While DMA is operating, registers at that level are write-protected.

Table 3.3 Export address addition value 
 DxWA(x=2−0)
 Contents
 000B
 do not add
 001B
 Add 2Bytes
 010B
 Add 4Bytes
 011B
 Add 8Bytes
 100B
 Add 16Bytes
 101B
 Add 32Bytes
 110B
 Add 64Bytes
 111B
 Add 128Bytes

There are regulations regarding this write address addition value as shown in Figure 3.6. As shown in this diagram, communication between the SCU and B-Bus is in 32-bit units, but communication between the B-Bus and the processor is in 16-bit units. Therefore, as shown in Figure 3.7, when transferring data A to D from the SCU to the processor, the SCU can transfer A to D at once to the B-Bus, but the B-Bus is However, the only option is to divide it into A to B and C to D and transfer it. From this, the B-Bus write address addition value is in units of 2 Bytes, so the difference between address 2 and address 1 can be specified as the write address addition value, as shown in Figure 3.8.

Figure 3.6 Communication unit between SCU and processor

Figure 3.7 Specific example of transfer between SCU and processor

Figure 3.8 Specifying the write address addition value

Address 1 - Address 2 can be specified with "Write address addition value"

＜ Limitations regarding addition value registers＞

Limitation of DMA read address addition value by access address
The value that can be set as the read address addition value changes depending on the address to be accessed. This also applies to DSP DMA instructions.

External area 4 area (A-Bus I/O area) → 0b,1b settings are possible
Others → Only setting 1b is possible

Setting value of address addition value bit when setting DMA read address update bit
When the read address update bit is "1b", the read address addition value bit must be "1b".

Restrictions on the address to access the DMA write addition value
The values that can be set for the write address addition value vary depending on the address being accessed. This also applies to DSP DMA instructions.

WORKRAM-H → 010b setting is possible
External areas 1 to 3 → 010b setting is possible
External area 4 area (A-Bus I/O area) → 000b,010b can be set
VDP1,VDP2,SCSP → All settings are possible

Setting value of address addition value bit when setting DMA write address update bit
When the DMA write address update bit is "1b", the write address addition value bit must be set as shown below depending on the bus space to be accessed.

External area 1 to 4 area (A-Bus) → 010b setting is possible
VDP1,VDP2,SCSP(B-Bus) → 001b can be set
WORKRAM-H(C-Bus) → 010b setting is possible

◆DMA permission register

This is a register that allows DMA execution. While DMA is operating, registers at that level are write-protected. Figure 3.9 shows the format of this register.

Figure 3.9 Level 2-0 DMA permission bit (register: D0EN, D1EN, D2EN) initial value 00000000H
bit 
31
  
  
  
  
  
  
24
 
23
  
  
  
  
  
  
16
 
15
  
  
  
  
  
  
8 
7 
  
  
  
  
  
  
0 
25FE0010 (Level 0)
25FE0030 (Level 1)
25FE0050 (Level 2)
 − − − − − − − − − − − − − − − − − − − − − − − １ − − − − − − − ２

DMA permission bit ( 1 [bit 8] in Figure 3.9 )
DxEN[x=2-0](W) DMA level 2-0 ENable bit
This bit allows execution of DMA. Set this flag to 1 to allow DMA. After this, DMA will be able to start, so please set other necessary data in advance.

DMA start bit ( 2 [bit 0] in Figure 3.9 )
DxGO[x=2-0](W) DMA level 2-0 GO bit
This bit starts DMA execution. This bit is valid only when the activation factor bit is 111B. Set this bit to 1 to activate DMA. One set causes DMA to be activated once.

◆DMA mode, address update, activation factor selection register

This register specifies the DMA mode (direct or indirect mode), address update (setting value retention or update), and activation factor selection. Figure 3.10 shows details of this register. While DMA is operating, registers at that level are write-protected.

Figure 3.10 Level 2-0 DMA mode, address update, activation factor selection register (registers: D0MD, D1MD, D2MD) Initial value 00000007H
bit 
31
  
  
  
  
  
  
24
 
23
  
  
  
  
  
  
16
 
15
  
  
  
  
  
  
8 
7 
  
  
  
  
  
  
0 
25FE0014 (Level 0)
25FE0034 (Level 1)
25FE0054 (Level 2)
 − − − − − − − １ − − − − − − − ２ − − − − − − − ３ − − − − − ４ ５ ６

DMA mode bit ( 1 [bit 24] in Figure 3.10 )
DxMOD[x=2-0](W) DMA level 2-0 MODe bit
Determines the DMA mode. 0 indicates direct mode, 1 indicates indirect mode.

Read address update bit ( 2 [bit 16] in Figure 3.10 )
DxRUP[x=2-0](W) DMA level 2-0 Read address renewal UP bit
Determines whether to retain or update the value at the time of setting for the read address. 0 means retain, 1 means update. For details on operation, see the specific use case in Section 2.1, `` DMA Transfer .''

Write address update bit ( 3 [bit 8] in Figure 3.10 )
DxWUP[x=2-0](W) DMA level 2-0 Write address renewa UP bit
Determine whether to retain or update the value set for the export address. 0 means retain, 1 means update. For details on operation, see the specific use case in Section 2.1, `` DMA Transfer .''

DMA activation factor selection bits ( 4 to 6 [bits 2 to 0] in Figure 3.10 )
DxFT2-0[x=2-0](W) DMA level 2-0 starting FacTor bit2-0
DMA is activated by setting the DMA enable bit and receiving the external signal selected by the activation factor selection bit. However, when the activation factor bit is 111B, DMA is activated by setting the DMA activation bit.

Table 3.4 Activation factor details 
 Activation factor bit (x=2−0)
 Trigger factor
 DxFT2
 DxFT1
 DxFT0
 0
 0
 0
 Set enable bit and receive V-Blank-IN signal
 0
 0
 1
 Set enable bit and receive V-Blank-OUT signal
 0
 1
 0
 Set enable bit and receive H-Blank-IN signal
 0
 1
 1
 Set permission bit and receive timer 0 signal
 1
 0
 0
 Set enable bit and receive timer 1 signal
 1
 0
 1
 Setting the permission bit and receiving the Sound-Req signal
 1
 1
 0
 Set permission bit and receive sprite drawing end signal
 1
 1
 1
 Setting permission bits and setting DMA activation bits

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★ HARDWARE Manual ★ SCU User's Manual ★ 3.1 Register List
Copyright SEGA ENTERPRISES, LTD., 1997