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★ HARDWARE Manual ★ SCU User's Manual ★ 3.1 Register List
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SCU User's Manual/Chapter 3 Register details

■3.6 A-Bus control register

◆A-Bus interrupt acknowledge register

Figure 3.23 shows details of the A-Bus interrupt acknowledge register.

Figure 3.23 A-Bus interrupt acknowledge register (register: AIAK) initial value 00000000H
bit 
31
  
  
  
  
  
  
24
 
23
  
  
  
  
  
  
16
 
15
  
  
  
  
  
  
8 
7 
  
  
  
  
  
  
0
25FE00BC − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − １

A-Bus interrupt acknowledge ( 1 [bit 0] in Figure 3.23 )
AIACK(R/W) A-Bus Interrupt ACKnowledge
Indicates enable/disable of interrupts from devices existing on A-Bus. This bit is a read/write bit. Table 3.9 shows the meaning of the bits. When an interrupt is requested, an A-Bus interrupt acknowledge cycle is generated, the interrupt type data (16 bits) is loaded, and the current interrupt status can be recognized from the contents. When this cycle occurs, the AIACK bit becomes 0 and A-Bus interrupts are disabled, so the AIACK bit must be reset to accept further interrupts from A-Bus.

Table 3.9 A-Bus interrupt acknowledge contents 
 access
 situation
 Contents
 loading
 0
 A-Bus interrupt disabled
 1
 A-Bus interrupt enabled
 Start writing
 0
 A-Bus interrupt disabled
 1
 A-Bus interrupt enabled

◆A-Bus setting register

There are a total of four types of spaces connected to the A-Bus: three types of spaces for chip select (hereinafter referred to as CS) 0-2, and one spare space where CS is not output. I am.
The A-Bus registers are determined by the connected device and must be set to include all devices. After setting, please do not change the value unnecessarily.

●CS0,1,2, spare space A-Bus setting register
Figure 3.24 shows the details of the A-Bus setting registers for the CS0 space and CS1 space, and Figure 3.24 shows the details of the A-Bus setting registers for the CS2 space and spare space.

Figure 3.24 A-Bus setting register [CS0,1 space] (Register: ASR0) Initial value 00000000H
bit 
31
  
  
  
  
  
  
24
 
23
  
  
  
  
  
  
16
 
15
  
  
  
  
  
  
8 
7 
  
  
  
  
  
  
0
25FE00B0 − ２ ３ ４ ５ ６ ７ ８ ９ 10 11 12 13 14 − 15 − 17 18 19 20 21 22 23 24 25 26 27 28 29 − 30

Figure 3.25 A-Bus setting register [CS2, spare space] (Register: ASR1) Initial value 00000000H
bit 
31
  
  
  
  
  
  
24
 
23
  
  
  
  
  
  
16
 
15
  
  
  
  
  
  
8 
7 
  
  
  
  
  
  
0
25FE00B4 − ２ ３ ４ − − − − − − − − ５ ６ − ７ − ９ 10 11 12 13 14 15 16 17 18 19 20 21 − 22

CS0 space post-write precharge insertion bit ( 2 [bit 30] in Figure 3.24 )
A0WPC(W) A-Bus CS0 after Write Pre-Charge insert bit
After writing data to CS0 space, you can insert one clock worth of unprocessed state. This bit determines whether the process is enabled or disabled. 1 indicates enabled, 0 indicates disabled. This bit has no effect on the behavior of CS0 after reading space. Figure 3.27 shows the behavior when this bit is set.

Figure 3.27 Timing when setting the post-write precharge insertion bit

* The clock (CLK) in the diagram is the SCU's internal clock.

Precharge insertion bit after reading CS0 space ( 3 [bit 29] in Figure 3.24 )
A0RPC(W) A-Bus CS0 Read Pri-Charge insert bit
After reading the data in the CS0 space, you can insert one clock worth of unprocessed state. This bit determines whether the process is enabled or disabled. 1 indicates enabled, 0 indicates disabled. This bit has no effect on the behavior after writing CS0 space. Figure 3.28 shows the behavior when this bit is set.
Depending on the type of device, some devices require a certain period of time after setting CS to High before setting the next CS to Low, so set this bit. Do the same with writing.

Figure 3.28 Timing when setting precharge insertion bit after read

* The clock (CLK) in the diagram is the SCU's internal clock.

External weight valid bit in CS0 space ( 4 [bit 28] in Figure 3.24 )
A0EWT(W) A-Bus CS0 External Wait effective bit
When accessing the CS0 space via the A-Bus, a wait can be forced by an external signal, and this bit determines whether to enable or disable that processing. 1 indicates enabled, 0 indicates disabled. When enabled, SCU weight sampling continues to wait while the external wait signal is low. Figure 3.29 shows the difference in timing charts between when external waits are disabled and when they are enabled.

Figure 3.29 Timing difference due to external wait enable bit setting

* The clock (CLK) in the diagram is the SCU's internal clock.

Burst cycle wait number setting bits in CS0 space ( 5 to 8 [bits 27 to 24] in Figure 3.24 )
A0BW3-0(W) A-Bus CS0 Burst cycle Wait bit3-0
Set the number of waits per cycle when performing burst access in CS0 space. Table 3.10 shows the setting values.

Table 3.10 CS0 spatial burst cycle setting values 
 bit
 number of weights
 A0BW3
 A0BW2
 A0BW1
 A0BW0
 0
 0
 0
 0
 No weights (do not sample weights)
 0
 0
 0
 1
 1 cycle weight
 :
 :
 :
 :
 1
 1
 1
 0
 14 cycle weights
 1
 1
 1
 1
 15 cycle weights




 Normal cycle wait number setting bits in CS0 space ( 9 to 12 [bits 23 to 20] in Figure 3.24 )
 A0NW3-0(W) A-Bus CS0 Normal cycle Wait bit3-0
 Set the number of waits for one cycle when performing normal access in CS0 space. Table 3.11 shows the setting values.



 Table 3.11 CS0 space normal cycle setting values

 bit
 number of weights
 A0NW3
 A0NW2
 A0NW1
 A0NW0
 0
 0
 0
 0
 No weights (do not sample weights)
 0
 0
 0
 1
 1 cycle weight
 :
 :
 :
 :
 1
 1
 1
 0
 14 cycle weights
 1
 1
 1
 1
 15 cycle weights




 Burst length setting bits in CS0 space ( 13 to 14 [bits 19 to 18] in Figure 3.24 )
 A0LN1-0(W) A-Bus CS0 burst LeNgth bit1-0
 Specify the length (boundary) to access when performing burst access in CS0 space. Table 3.12 shows the length settings.



 Table 3.12 CS0 spatial burst length settings

 bit
 Access settings
 A0LN1
 A0LN0
 0
 0
 No burst access
 0
 1
 4 address burst access
 1
 0
 256 address burst access
 1
 1
 no boundaries




 CS0 space bus size setting bit ( 15 [bit 16] in Figure 3.24 )
 A0SZ(W) A-Bus CS0 bus SiZe bit
 Set the A-Bus bus size in CS0 space. Table 3.13 shows the setting values.



 Table 3.13 CS0 space bus size settings

 A0SZ
 Bus size setting value
 0
 Specify 16 bit bus
 1
 Specify 8 bit bus




 CS1 space post-write precharge insertion bit ( 17 [bit 14] in Figure 3.24 )
 A1WPC(W) A-Bus CS1 after Write Pre-Charge insert bit
 After writing data to CS1 space, you can insert one clock worth of unprocessed state. This bit determines whether the process is enabled or disabled. 1 indicates enabled, 0 indicates disabled. This bit has no effect on post-load behavior. See Figure 3.27 for the behavior when this bit is set.


 Precharge insertion bit after reading CS1 space ( 18 [bit 13] in Figure 3.24 )
 A1RPC(W) A-Bus CS1 Read Pre-Charge insert bit
 After reading the data in the CS1 space, you can insert one clock worth of unprocessed state. This bit determines whether the process is enabled or disabled. 1 indicates enabled, 0 indicates disabled. This bit has no effect on post-write behavior. See Figure 3.28 for the behavior when this bit is set.


 External weight valid bit in CS1 space ( 19 [bit 12] in Figure 3.24 )
 A1EWT(W) A-Bus CS1 External Wait effective bit
 When accessing the CS1 space via the A-Bus, weights can be forced by an external signal, and this bit determines whether to enable or disable that processing. 1 indicates enabled, 0 indicates disabled. When enabled, it continues to wait while the external signal is low. See Figure 3.29 for the difference in timing charts between when external waits are disabled and when they are enabled.


 Burst cycle wait number setting bits in CS1 space ( 20 to 23 [bits 11 to 8] in Figure 3.24 )
 A1BW3-0(W) A-Bus CS1 Burst cycle Wait bit3-0
 Set the number of waits per cycle when performing burst access in CS1 space. Table 3.14 shows the setting values.



 Table 3.14 CS1 spatial burst cycle setting values

 bit
 number of weights
 A1BW3
 A1BW2
 A1BW1
 A1BW0
 0
 0
 0
 0
 No weights (do not sample weights)
 0
 0
 0
 1
 1 cycle weight
 :
 :
 :
 :
 1
 1
 1
 0
 14 cycle weights
 1
 1
 1
 1
 15 cycle weights




 Normal cycle wait number setting bits in CS1 space ( 24 to 27 [bits 7 to 4] in Figure 3.24 )
 A1NW3-0(W) A-Bus CS1 Normal cycle Wait bit3-0
 Set the number of waits for one cycle when performing normal access in CS1 space. Table 3.15 shows the setting values.



 Table 3.15 CS1 spatial normal cycle setting values

 bit
 number of weights
 A1NW3
 A1NW2
 A1NW1
 A1NW0
 0
 0
 0
 0
 No weights (do not sample weights)
 0
 0
 0
 1
 1 cycle weight
 :
 :
 :
 :
 1
 1
 1
 0
 14 cycle weights
 1
 1
 1
 1
 15 cycle weights




 Burst length setting bits in CS1 space ( 28 to 29 [bits 3 to 2] in Figure 3.24 )
 A1LN1-0(W) A-Bus CS1 burst LeNgth bit1-0
 Specify the length (boundary) to access when performing burst access in CS1 space. Table 3.16 shows the length settings.



 Table 3.16 CS1 spatial burst length settings

 bit
 Access settings
 A1LN1
 A1LN0
 0
 0
 No burst access
 0
 1
 4 address burst access
 1
 0
 256 address burst access
 1
 1
 no boundaries




 CS1 space bus size setting bit ( 30 [bit 0] in Figure 3.24 )
 A1SZ(W) A-Bus CS1 bus SiZe bit
 Set the A-Bus bus size in CS1 space. Table 3.17 shows the setting values.



 Table 3.17 CS1 space bus size settings

 A1SZ
 Bus size setting value
 0
 Specify 16 bit bus
 1
 Specify 8 bit bus




 CS2 space post-write precharge insertion bit ( 2 [bit 30] in Figure 3.25 )
 A2WPC(W) A-Bus CS2 after Write Pri-Charge insert bit
 After writing data to CS2 space, you can insert one clock worth of unprocessed state. This bit determines whether the process is enabled or disabled. 1 indicates enabled, 0 indicates disabled. This bit has no effect on post-load behavior. See Figure 3.27 for the behavior when this bit is set.


 Precharge insertion bit after reading CS2 space ( 3 [bit 29] in Figure 3.25 )
 A2RPC(W) A-Bus CS2 Read Pri-Charge insert bit
 After reading the data in the CS2 space, you can insert one clock worth of unprocessed state. This bit determines whether the process is enabled or disabled. 1 indicates enabled, 0 indicates disabled. This bit has no effect on post-write behavior. See Figure 3.28 for the behavior when this bit is set.


 External weight valid bit in CS2 space ( 4 [bit 28] in Figure 3.25 )
 A2EWT(W) A-Bus CS2 External Wait effective bit
 When accessing CS2 space via A-Bus, weights can be forced by an external signal, and this bit determines whether to enable or disable that processing. 1 indicates enabled, 0 indicates disabled. When enabled, it continues to wait while the external signal is low. , see Figure 3.29 for the difference in timing chart between when external waits are disabled and when they are enabled.


 Burst length setting bits in CS2 space ( 5 to 6 [bits 19 to 18] in Figure 3.25 )
 A2LN1-0(W) A-Bus CS2 burst LeNgth bit1-0
 Specify the length (boundary) to access when performing burst access in CS2 space. Table 3.18 shows the length settings.



 Table 3.18 CS2 spatial burst length settings

 bit
 Access settings
 A2LN1
 A2LN0
 0
 0
 No burst access
 0
 1
 4 address burst access
 1
 0
 256 address burst access
 1
 1
 no boundaries




 CS2 space bus size setting bit ( 7 [bit 16] in Figure 3.25 )
 A2SZ(W) A-Bus CS2 bus SiZe bit
 Set the A-Bus bus size in CS2 space. Table 3.19 shows the setting values.



 Table 3.19 CS2 space bus size settings

 A2SZ
 Bus size setting value
 0
 Specify 16 bit bus
 1
 Specify 8 bit bus




 Precharge insertion bit after writing in spare space ( 9 [bit 14] in Figure 3.25 )
 A3WPC(W) A-Bus CS3 after Write Pri-Charge insert bit
 After writing data to the spare space, you can insert one clock worth of unprocessed state. This bit determines whether the process is enabled or disabled. 1 indicates enabled, 0 indicates disabled. This bit has no effect on post-load behavior. See Figure 3.27 for the behavior when this bit is set.


 Precharge insertion bit after reading spare space ( 10 [bit 13] in Figure 3.25 )
 A3RPC(W) A-Bus CS3 Read Pri-Charge insert bit
 After reading the data in the spare space, you can insert one clock worth of unprocessed state. This bit determines whether the process is enabled or disabled. 1 indicates enabled, 0 indicates disabled. This bit has no effect on post-write behavior. See Figure 3.28 for the behavior when this bit is set.


 External weight valid bit in spare space ( 11 [bit 12] in Figure 3.25 )
 A3EWT(W) A-Bus CS3 External WaiT effective bit
 When accessing the spare space via A-Bus, weights can be forced by an external signal, and this bit determines whether to enable or disable that processing. 1 indicates enabled, 0 indicates disabled. When enabled, it continues to wait while the external signal is low. , see Figure 3.29 for the difference in timing charts between when external waits are disabled and when they are enabled.


 Reserve space burst cycle wait number setting bits ( 12 to 15 [bits 11 to 8] in Figure 3.25 )
 A3BW3-0(W) A-Bus CS3 Burst cycle Wait bit3-0
 Set the number of waits per cycle when performing burst access in spare space. Table 3.20 shows the setting values.



 Table 3.20 Spare space burst cycle setting values

 bit
 number of weights
 A3BW3
 A3BW2
 A3BW1
 A3BW0
 0
 0
 0
 0
 No weights (do not sample weights)
 0
 0
 0
 1
 1 cycle weight
 :
 :
 :
 :
 1
 1
 1
 0
 14 cycle weights
 1
 1
 1
 1
 15 cycle weights




 Reserve space normal cycle wait number setting bits ( 16 to 19 [bits 7 to 4] in Figure 3.25 )
 A3NW3-0(W) A-Bus CS3 Normal cycle Wait bit3-0
 Set the number of waits per cycle when performing normal access in the spare space. Table 3.21 shows the setting values.



 Table 3.21 Spare space normal cycle setting values

 bit
 number of weights
 A3NW3
 A3NW2
 A3NW1
 A3NW0
 0
 0
 0
 0
 No weights (do not sample weights)
 0
 0
 0
 1
 1 cycle weight
 :
 :
 :
 :
 1
 1
 1
 0
 14 cycle weights
 1
 1
 1
 1
 15 cycle weights




 Reserve space burst length setting bits ( 20 to 21 [bits 3 to 2] in Figure 3.25 )
 A3LN1-0(W) A-Bus CS3 burst LeNgth bit1-0
 Specify the length (boundary) to access when performing burst access in the spare space. Table 3.22 shows the length settings.



 Table 3.22 Spare space burst strength settings

 bit
 Access settings
 A3LN1
 A3LN0
 0
 0
 No burst access
 0
 1
 4 address burst access
 1
 0
 256 address burst access
 1
 1
 no boundaries




 Spare space bus size setting bit ( 22 [bit 0] in Figure 3.25 )
 A3SZ(W) A-Bus CS3 bus SiZe bit
 Set the A-Bus bus size in the spare space. Table 3.23 shows the setting values.



 Table 3.23 Spare space bus size settings

 A3SZ
 Bus size setting value
 0
 Specify 16 bit bus
 1
 Specify 8 bit bus




 ◆A-Bus refresh register
 Figure 3.30 shows details of the A-Bus refresh register.
 Figure 3.30 A-Bus refresh register (register: AREF) initial value 00000010H
	
bit

31
  
  
  
  
  
  
24


23
  
  
  
  
  
  
16


15
  
  
  
  
  
  
8 


7 
  
  
  
  
  
  
0 


 25FE00A0
  −	
  −
  −
  −	
  −	
  −
  −
  −	
  −	
  −
  −
  −	
  −	
  −
  −
  −	
  −	
  −
  −
  −	
  −	
  −
  −
  −	
  −	
  −
  −
  １	
  ２	
  ３
  ４
  ５	







 A-Bus refresh output valid bit ( 1 [bit 4] in Figure 3.30 )
 ARFEN(W) A-Bus ReFresh ENable bit
 Enables A-Bus refresh cycle output. Valid with "1". The initial value of this bit at power-on reset is "1".




 Prevents user modification of the A-Bus refresh output enable bit.




 A-Bus refresh wait number setting bits ( 2 to 5 [bits 3 to 0] in Figure 3.30 )
 ARWT3-0(W) A-Bus Refresh Wait bit3-0
 Set the number of waits for the A-Bus refresh cycle. Details are shown in Table 3.24.



 Table 3.24 A-Bus refresh wait number

 bit
 number of weights
 ARWT3
 ARWT2
 ARWT1
 ARWT0
 0
 0
 0
 0
 don't weight
 0
 0
 0
 1
 1 cycle weight
 :
 :
 :
 :
 1
 1
 1
 0
 14 cycle weights
 1
 1
 1
 1
 15 cycle weights




 ◆Restrictions when using A-Bus
 Precautions when using flash memory on A-Bus
 When using flash memory on the A-Bus, if software waits between writes, if an interrupt or DMA occurs midway and the write-to-write period exceeds the flash memory specifications and becomes longer, operation is guaranteed. This will no longer be the case.

 Therefore, when using flash memory under the conditions described above, interrupts and DMA must be disabled.


 Similar precautions should be taken when using power memory.


 Restrictions when using A-Bus areas other than ACS2 as an 8-bit bus
 When using an area other than CS2 of A-Bus as an 8-bit bus, writing a bus to the 8-bit bus area may cause an abnormal cycle in which only ACS becomes active.

 This occurs when a byte is written to address 4n+2 (n is an integer) in the 8-bit bus area after reading or writing to the 16-bit bus area. ”, ARD, AWRO, and AWR1 are “inactive” and the data bus is “output”.

 In order to prevent such abnormal conditions from occurring, if areas other than CS2 of the A-Bus are assigned to an 8-bit bus, one of the following restrictions will be required.


    

  1. 
 When a byte write to an 8-bit bus area and a read or write to a 16-bit bus area are performed alternately, a condition is required that an interrupt DMA or the like does not occur unexpectedly.
    
 → Disable interrupts and DMA
    

  2. 
 Writes to the 8-bit bus area are limited to word writes.
  3. 
 The 8-bit bus area is write-read only.
  4. 
 Writing to address 4n+2 (n is an integer) to an 8-bit bus is prohibited.





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