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★ HARDWARE Manual ★ SCU User's Manual ★ 3.1 Register List
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SCU User's Manual/Chapter 3 Register Details

■3.5 Interrupt control register

◆Interrupt mask register

Figure 3.21 shows details of the interrupt mask register. When the register value is 0, interrupts are not masked, and when the register value is 1, interrupts are masked.

Figure 3.21 Interrupt mask register (register: IMS) Initial value 0000BFFFH
bit 
31
　
　
　
　
　
　
24
 
23
　
　
　
　
　
　
16
 
15
　
　
　
　
　
　
8 
7 
　
　
　
　
　
　
0
25FE00A0 − − − − − − − − − − − − − − − − １ − ２ ３ ４ ５ ６ ７ ８ ９ 10 11 12 13 14 15

A-Bus interrupt mask bit ( 1 [bit 15] in Figure 3.21 )
IMS15(W) Interrupt MaSk bit bit15
Specify whether to mask A-Bus interrupts.

Note
 Be sure to mask (set to 1) the A-Bus interrupt mask bit except for controlling special cartridge-connected devices.

supplement
"Special cartridge equipment" refers to "XBAND modem" and "NetLink modem". Applications using these devices should not mask A-Bus external interrupts.

Sprite drawing end interrupt mask bit ( 2 [bit 13] in Figure 3.21 )
IMS13(W) Interrupt MaSk bit bit13
Specify whether to mask interrupts when sprite drawing ends.

DMA illegal interrupt mask bit ( 3 [bit 12] in Figure 3.21 )
IMS12(W) Interrupt MaSk bit bit12
Specify whether to mask DMA illegal interrupts.

Level 0-DMA end interrupt mask bit ( 4 [bit 11] in Figure 3.21 )
IMS11(W) Interrupt MaSk bit bit11
Specify whether to mask level 0-DMA end interrupts.

Level 1-DMA end interrupt mask bit ( 5 [bit 10] in Figure 3.21 )
IMS10(W) Interrupt MaSk bit bit10
Specify whether to mask the level 1-DMA end interrupt.

Level 2-DMA end interrupt mask bit ( 6 [bit 9] in Figure 3.21 )
IMS9(W) Interrupt MaSk bit bit9
Specify whether to mask level 2-DMA end interrupts.

PAD interrupt mask bit ( 7 [bit 8] in Figure 3.21 )
IMS8(W) Interrupt MaSk bit bit8
Specify whether to mask interrupts from PAD.

System manager interrupt mask bit ( 8 [bit 7] in Figure 3.21 )
IMS7(W) Interrupt MaSk bit bit7
Specify whether to mask interrupts from the system manager.

Sound request interrupt mask bit ( 9 [bit 6] in Figure 3.21 )
IMS6(W) Interrupt MaSk bit bit6
Specify whether to mask sound request interruptions.

SP end interrupt mask bit ( 10 [bit 5] in Figure 3.21 )
IMS5(W) Interrupt MaSk bit bit5
Specify whether to mask the DSP end interrupt.

Timer-1 interrupt mask bit ( 11 [bit 4] in Figure 3.21 )
IMS4(W) Interrupt MaSk bit bit4
Specify whether to mask timer-1 interrupts.

Timer-0 interrupt mask bit ( 12 [bit 3] in Figure 3.21 )
IMS3(W) Interrupt MaSk bit bit3
Specify whether to mask timer-0 interrupts.

H-blank-IN interrupt mask bit ( 13 [bit 2] in Figure 3.21 )
IMS2(W) Interrupt MaSk bit bit2
Specify whether to mask H-Blank-IN interrupts.

V-blank-OUT interrupt mask bit ( 14 [bit 1] in Figure 3.21 )
IMS1(W) Interrupt MaSk bit bit1
Specify whether to mask V-Blank-OUT interrupts.

V-blank-IN interrupt mask bit ( 15 [bit 0] in Figure 3.21 )
IMS0(W) Interrupt MaSk bit bit0
Specify whether to mask V-Blank-IN interrupts.

◆Interrupt status register

Figure 3.22 shows details of the interrupt status register.

Figure 3.22 Interrupt status register (register: IST) Initial value 00000000H
bit 
31
　
　
　
　
　
　
24
 
23
　
　
　
　
　
　
16
 
15
　
　
　
　
　
　
8 
7 
　
　
　
　
　
　
0
25FE00A4 １ ２ ３ ４ ５ ６ ７ ８ ９ 10 11 12 13 14 15 16 − − 17 18 19 20 21 22 23 24 25 26 27 28 29 30

When writing to the interrupt status register, bits that should be set to indicate that an interrupt has occurred may not be set. Therefore, writing to this register is prohibited.

Table 3.8 Interrupt status bit contents (R)
situation Contents
0 no interrupt has occurred
1 An interrupt is occurring

External interrupt status bits ( 1 to 16 [bit31 to 16] in Figure 3.22 )
IST31-16(R) Interrupt STatus bit bit31-16
Indicates the status of 16 external interrupts from external interrupt 15 (1 in the figure) to external interrupt 0 (16 in the figure).

Sprite drawing end interrupt status bit ( 17 [bit 13] in Figure 3.22 )
IST13(R) Interrupt STatus bit bit13
Represents the interrupt status at the end of sprite drawing.

DMA illegal interrupt status bit ( 18 [bit 12] in Figure 3.22 )
IST12(R) Interrupt STatus bit bit12
Indicates the status of DMA illegal interrupt.

Level 0-DMA end interrupt status bit ( 19 [bit 11] in Figure 3.22 )
IST11(R) Interrupt STatus bit bit11
Level 0 - Represents the status of the DMA end interrupt.

Level 1-DMA end interrupt status bit ( 20 [bit 10] in Figure 3.22 )
IST10(R) Interrupt STatus bit bit10
Level 1 - Represents the status of the DMA end interrupt.

Level 2-DMA end interrupt status bit ( 21 [bit 9] in Figure 3.22 )
IST9(R) Interrupt STatus bit bit9
Level 2 - Represents the status of the DMA end interrupt.

PAD interrupt status bit ( 22 [bit 8] in Figure 3.22 )
IST8(R) Interrupt STatus bit bit8
Indicates the status of interrupts from PAD.

System manager interrupt status bit ( 23 [bit 7] in Figure 3.22 )
IST7(R) Interrupt STatus bit bit7
Represents the status of interrupts from the system manager.

Sound request interrupt status bit ( 24 [bit 6] in Figure 3.22 )
IST6(R) Interrupt STatus bit bit6
Represents the interrupt status of a sound request.

DSP end interrupt status bit ( 25 [bit 5] in Figure 3.22 )
IST5(R) Interrupt STatus bit bit5
Indicates the status of the DSP end interrupt.

Timer-1 interrupt status bit ( 26 [bit 4] in Figure 3.22 )
IST4(R) Interrupt STatus bit bit4
Represents the status of timer-1 interrupt.

Timer-0 interrupt status bit ( 27 [bit 3] in Figure 3.22 )
IST3(R) Interrupt STatus bit bit3
Represents the status of timer-0 interrupt.

H-blank-IN interrupt status bit ( 28 [bit 2] in Figure 3.22 )
IST2(R) Interrupt STatus bit bit2
H-Blank-Indicates the interrupt status of IN. .

V-blank-OUT interrupt status bit ( 29 [bit 1] in Figure 3.22 )
IST1(R) Interrupt STatus bit bit1
Represents the interrupt status of V-Blank-OUT.

V-blank-IN interrupt status bit ( 30 [bit 0] in Figure 3.22 )
IST0(R) Interrupt STatus bit bit0
Indicates the interrupt status of V-Blank-IN.

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