<12/31>SCU User's Manual/Chapter 3/■3.4 Timer Register

★ HARDWARE Manual ★ SCU User's Manual ★ 3.1 Register List

▲ Back ｜ Forward ▼

SCU User's Manual/Chapter 3 Register details

■3.4 Timer register

◆Timer 0 compare register

Figure 3.18 shows details of the timer 0 compare register. (Timer 0 is a counter that counts up when receiving the H-Blank-IN signal and is cleared when receiving the V-Blank-END signal.)

Figure 3.18 Timer 0 compare register (register: T0C) initial value undefined
bit
31

24

23

16

15

8

7

0

25FE0090 − − − − − − − − − − − − − − − − − − − − − − １２３４５６７８９ 10

Timer 0 compare data ( 1 to 10 [bit 9 to 0] in Figure 3.18 )

T0C9-0(W) Timer 0 Compare data bit9-0

When the value of timer 0 becomes equal to the value of this register, a timer 0 interrupt is generated.

＜ Notes on using timer 0 compare register＞

It is possible to set 10-bit data, but if impossible data is set, no interrupt will occur. Be sure to set a value within the usable range.

For example, in the case of NTSC non-interlaced (263 lines per screen, 224 effective lines), an interrupt will occur as shown below.

T0C9-0
=1
Occurs at the beginning of HBLANK-IN immediately before the first line of the effective screen

T0C9-0
=2
Occurs at the beginning of HBLANK-IN immediately before the first two lines of the active screen

T0C9-0
=224
Occurs at the beginning of HBLANK-IN just before the last line of the effective screen

T0C9-0
=225
Occurs at the beginning of HBLANK-IN immediately after the valid screen ends

T0C9-0
=263
Occurs at the beginning of HBLANK-IN immediately before the start of the valid screen.

T0C9-0
= 264~1023
no interrupt occurs

T0C9-0
=0
Interrupt occurs at the same timing as VBLANK-OUT

◆Timer 1 set data register

Figure 3.19 shows details of the timer 1 set data register. (Timer 1 sets the data in this register upon receiving the H-blank-IN signal, automatically counts down at 7MHz, and issues an interrupt when the value of timer 1 reaches 0.)

Figure 3.19 Timer 1 set data register (register: T1S) Initial value undefined
bit
31

24

23

16

15

8

7

0

25FE0094 − − − − − − − − − − − − − − − − − − − − − − − １２３４５６７８９

Timer 1 set data ( 1 to 9 [bits 8 to 0] in Figure 3.19 )

T1S8-0(W) Timer 1 Set data bit8-0

Set the value set to timer 1.

＜ Notes on using the timer 1 set data register＞

The value of the timer 1 set data register is loaded into timer 1 when ``timer 1 is stopped and HBLANK-IN occurs''.
If data larger than 1 line is set in the timer 1 set data register, timer 1 interrupts will not occur every line.

[Count range]
For 1 line 320 dots 1~1AAH

For 1 line 352 dots 1~1C6H

For 1 line 424 dots 1~D3H

For 1 line 426 dots 1～D4H

**[Count range]**
For 1 line 320 dots	1~1AAH
For 1 line 352 dots	1~1C6H
For 1 line 424 dots	1~D3H
For 1 line 426 dots	1～D4H

(Please note that if you specify the count number 0, it will be 512.)

◆Timer 1 mode register

Figure 3.20 shows details of the timer 1 mode register. This register determines how to set timer 1 generation.

Figure 3.20 Timer 1 mode register (register: T1MD) Initial value 00000000H
bit
31

24

23

16

15

8

7

0

25FE0098 − − − − − − − − − − − − − − − − − − − − − − − １ − − − − − − − ２

Timer 1 mode bit ( 1 [bit 8] in Figure 3.20 )

T1MD(W) Timer 1 MoDe bit

This bit is used to specify the occurrence of timer 1. Table 3.6 shows the details of the occurrence.

**Table 3.6 Timer 1 generation selection details**
T1MD	Occurrence selection content
0	An interrupt occurs on every line.
1	Occurs only on the line specified by timer 0.

Timer enable bit ( 2 [bit 0] in Figure 3.20 )

TENB(W) Timer ENaBle bit

This bit turns the timer operation ON/OFF. Table 3.7 shows the operation details.

**Table 3.7 Timer operation details**
TENB	Timer operation
0	Timer operation OFF
1	Timer operation ON

▲ Back ｜ Forward ▼

★ HARDWARE Manual ★ SCU User's Manual ★ 3.1 Register List

bit	31							24	23							16	15							8	7							0
25FE0090	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	１	２	３	４	５	６	７	８	９	10

T0C9-0	=1	Occurs at the beginning of HBLANK-IN immediately before the first line of the effective screen
T0C9-0	=2	Occurs at the beginning of HBLANK-IN immediately before the first two lines of the active screen
T0C9-0	=224	Occurs at the beginning of HBLANK-IN just before the last line of the effective screen
T0C9-0	=225	Occurs at the beginning of HBLANK-IN immediately after the valid screen ends
T0C9-0	=263	Occurs at the beginning of HBLANK-IN immediately before the start of the valid screen.
T0C9-0	= 264~1023	no interrupt occurs
T0C9-0	=0	Interrupt occurs at the same timing as VBLANK-OUT

bit	31							24	23							16	15							8	7							0
25FE0094	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	−	１	２	３	４	５	６	７	８	９