Reflected in manual

"HARDWARE MANUAL" SCU User's Manual

1. Disable writing to A-Bus by SCU-DMA

2. Prohibition of reading by SCU-DMA from VDP2 area

3. Write access to the VDP1 register is performed in word (2 byte) units.

4. SCU-DMA cannot be used for WORKRAM-L (Note)

5. Always use cache-through address to access SCU registers

6. Writing to unused areas (address 25FE00ACH, etc.) is prohibited.

7. Disable writing to interrupt status register (25FE00A4H)

8. A-Bus←→Prohibition of access to A-Bus and B-Bus from the CPU during B-Bus DMA operation

9. Prohibition of setting A-Bus look-ahead enable bit

10. A-Bus interrupt acknowledge register address change (address 25FE00A8H)

11. A-Bus configuration register write restrictions

12. Waiting for SCU-DMA startup of A-Bus←→B-Bus when CPU writes to A-Bus and B-Bus

13. Delete DMA status register (address 25FE0070H to 25FE007CH)

14. DMA forced stop register function deletion (address 25FE0060H)

15. Disable reading the number of transferred bytes in the DMA transfer register (write only)

16. Limitation of DMA read address addition value by access address

17. Value of address addition value bit when setting DMA read address update bit

18. Limitation of DMA write address addition value by access address

19. Value of address addition value bit when DMA write address update bit is set

20. DMA channels can be used simultaneously: 2 channels

21. Specification change of DMA startup method

22. Specifications when a DMA activation trigger occurs during DMA execution

23. Disable writing to registers at the corresponding level during DMA activation

24. No DMA illegal interrupt occurs during DMA execution in indirect mode

25. DMA indirect mode table specification change

26. Clear the program end interrupt flag when starting the DSP

27. Limitation of address addition value when transferring DSP DMA instruction from B-Bus to DSP DATA RAM

28. When debugging with ICE, DMA operation becomes slow when BREAK is performed.

29. Be sure to enable BREQ when debugging with ICE

30. Notes on using timer 0 compare register (address 25FE0090H)

31. Notes on using the timer 1 set register (address 25FE0094H)

32. Notes on read access to A-Bus and B-Bus areas (2000000H to 5FFFFFFH)

33. Initializing A-Bus refresh at POWER ON RESET (address 25FE00B8H)

34. Initial value of SDRAM selection bit (address 25FE00C4 _H )

35. Prohibition of starting DMA level 2 while DMA level 1 is running

36. Precautions when reading the DSP program control port (address _25FE0080H )