SCSP User's Manual/Table of Contents

★ HARDWARE Manual ★ SCSP User's Manual

SCSP User's Manual

Index

alphabetic index

[Number] [A] [C] [D] [E] [F] [I] [K] [L] [M] [O] [P] [R] [ S] [T]

▲ [Number]

Correspondence between 3-bit code and register

4SLOT configuration algorithm

7SLOT FM configuration

D/A converter output level

Send level to D/A converter

Localization data by DIPAN

DMA controller block diagram

DMA transfer register

DMA transfer direction

DMA transfer interface

DSP configuration

DSP configuration diagram

DSP output stage adjustment section

DSP control register

DSP input stage calculation adjustment section

Localization calculation using DSP

DSP micro program

DSP micro program map

Localization data by EFPAN

FM configuration algorithm pattern

FM sound source configuration diagram

FM sound source method

Address pointer output value when executing FM voice synthesis

Address displacement during FM synthesis

FM modulation control register

FNS.OCT parameter table

Relationship between the number of sources that can be input to IMXL and MIXS

KEY_ON and KEY_OFF sequences

AM modulation waveform by LFO

PM modulation waveform by LFO

LFO block diagram

LSI specifications

MDL modulation depth

Relationship between MDXSL/MDYSL and slots

Calculation formula for MDXSL/MDYSL

MIDI-I/F block diagram

MIDI OUT section and interrupt generation section

Relationship between OCT and FNS

PCM sound source

RBL and ring buffer length

SCSP LSI specifications

SCSP common control register (diagram)

SCSP common control register (list)

SCSP chip block diagram

Connecting SCSP and DAC

Operation of DSP in SCSP

SCSP memory map

Features of SSCTL

Count cycle for TACTL, TBCTL, and TCCTL setting values

TL, attenuation, and waveform amplitude

Wave data when TL bit4=1

Hiragana index

【A】【か】【さ】【TA】【な】【は】【ま】【RA】【Wow】

▲【A】: Access overview; Attack status; Transition from attack state to decay 1; KEY-OFF during attack state transition; Address pointer; Enlarged view of address pointer output; Phase adder; Interface (SCSP); Interface (sound CPU); Interface (main CPU); Interpolator; Effect data; Envelope generator; Sound data stack; Alternative loop; Sound source register; Sound source register allocation; Volume register
▲[ka]: External input; Register address of EFSDL and EFPAN corresponding to each EFSDL and EXTS; Career; Clipping processing; Wave data during clipping process; Change in attenuation
▲【SA】: Final stage output adjustment section; Top slot definition; Minimum and maximum interrupt time; Sound CPU address 100400H,100401H; Sound CPU Interface; Sound CPU specifications; Interrupt vector table for sound CPU; Sound system configuration; Starting the sound system; Sound stack; Sound data type; Sound memory configuration register; Sound memory map; Sound interrupt signal connection diagram@; Number of samples; System configuration; Frequency address pointer output value; Output mixer; Degree of amplitude and frequency modulation; Time difference until slot is written to sound stack; Slot status register; Slot connection formula; Number of slot connections; Slot block diagram; Slot averaging calculation; Slot-specific control register; Self feedback; Self-feedback modulation; cents; Real frequency for cents
▲[Ta]: Timer A increment period; Timer B increment period; Timer C increment period; Timer register; Direct audio adjustment section; Direct component and effect component path; Direct data; Multi-stage feedback; Decay 1 state; Decay 2 state; KEY-OFF during decay state transition; Digital mixer block diagram; Digital mixer block diagram
▲[NA]: Block diagram related to noise generation and relationship between LFO; Normal loop
▲【は】: Waveform RAM; Waveform address generation calculation section; Waveform address generation/waveform data reading; Waveform address pointer; Waveform data buffer; Maximum displacement by waveform read address; Oscillator oscillation frequency; Panpot; Phase generator; Combined feedback; Composite modulation; Prescaler; Averaging calculation unit; Averaging calculation formula
▲[Ma]: Mix register input level; Main CPU interface; Regarding communication between the main block and the sound block; Memory access priority; Memory address mapping diagram; Memory controller; Memory capacity; Modulation level; Modulator
▲[ra]: Reset vector; Linear; Reverse loop; Release status; Loop control register; Loop types; Loop waveform; Maximum address displacement by register setting value; Modulation degree by register setting value; Register map; Level calculation section; Level multiplier
▲【Wow】: Interrupt signal; Interrupt control register; Interrupt relations; Interrupt register bit correspondence; Interrupt register bit factor; Interrupt level setting register format

★HARDWARE Manual ★SCSP User's Manual

Copyright SEGA ENTERPRISES, LTD., 1997