Table of contents

table

Chapter 1 Sound system configuration

Table 1.1 Sound memory mapping (overview)

Table 1.2 Initialization setting data after reset

Table 1.3 Reset vector

Table 1.4 Interrupt vector table for sound CPU

Table 1.5 Register setting table

Chapter 4 SCSP register

Table 4.1 Address map by slot

Table 4.2 Control registers by slot

Table 4.3 SCSP common control register

Table 4.4 Sound data stack

Table 4.5 DSP Control Register

Table 4.6 DSP microprogram

Table 4.7 DSP buffer map

Table 4.16 Relationship between MDXSL/MDYSL and slots

Table 4.10 Maximum address displacement by register setting value

Table 4.18 TL, attenuation and waveform amplitude

Table 4.12 Actual frequency versus number of cents

Table 4.13 FNS.OCT parameter table

Table 4.14 Oscillator oscillation frequency

Table 4.15 AM modulation waveform by LFO

Table 4.16 PM modulation waveform by LFO

Table 4.17 Degree of amplitude modulation and frequency modulation

Table 4.18 Relationship between the number of sources that can be input to IMXL and MIXS

Table 4.19 Mix stack register input level

Table 4.20 D/A converter output level

Table 4.21 Localization data by DIPAN

Table 4.22 Send level to D/A converter

Table 4.23 Localization data by EFPAN

Table 4.24 Register address of EFSDL and EFPAN corresponding to each EFREG and EXTS

Table 4.25 Memory capacity

Table 4.26 Increment period of timer A

Table 4.27 Increment period of timer B

Table 4.28 Increment period of timer C

Table 4.29 Count period for TACTL, TBCTL, TCCTL setting values

Table 4.30 Shortest interrupt time and longest interrupt time

Table 4.31 Interrupt register bit factors

Table 4.32 DMA transfer direction

Table 4.33 DMA transfer

Table 4.34 RBL and ring buffer length

figure

Chapter 1 Sound system configuration

Figure 1.1 Sound block

Chapter 2 SCSP Overview

Figure 2.3 Reset sequence (operation order diagram)

Figure 2.4 Interrupt relationship

Figure 3.1 CD-DA pathway

Figure 2.1 SCSP chip block diagram

Chapter 3 SCSP function

Figure 3.1 Access overview

Figure 3.2 Memory access priority

Chapter 4 SCSP register

Figure 4.1 SCSP memory map (1906Word)

Figure 4.2 KEY_ON and KEY_OFF functions

Figure 4.3 Block diagram related to noise generation and relationship between LFO

Figure 4.4 Types of loops

Figure 4.5 Loop waveform

Figure 4.6 KEY_OFF during attack state transition

Figure 4.7 KEY-OFF during decay state transition

Figure 4.8 Change in attenuation

Figure 4.9 Transition from attack state to decay 1 (1)

Figure 4.10 Transition from attack state to decay 1 (2)

Figure 4.11 Transition from attack state to decay 1 (3)

Figure 4.12 Slot block diagram

Figure 4.13 Waveform address generation calculation section

Figure 4.14 Waveform address generation/waveform data reading

Figure 4.15 Enlarged view of address pointer output

Figure 4.16 Frequency address pointer output value

Figure 4.17 Address pointer output value when executing FM voice synthesis (1)

Figure 4.18 Address pointer output value when executing FM voice synthesis (2)

Figure 4.19 Normal loop

Figure 4.20 Reverse loop

Figure 4.21 Alternative loop

Figure 4.22 FM sound source configuration diagram

Figure 4.23 Averaging operation formula

Figure 4.24 Slot calculation and sound stack status

Figure 4.25 Time difference until slots are written to the sound stack

Figure 4.26 Slot averaging operation

Figure 4.27 Algorithm for 4-slot configuration

Figure 4.28 Slot 0 algorithm

Figure 4.29 Slot 2 algorithm

Figure 4.30 Slot 2 algorithm (by input slot)

Figure 4.31 Slot 3 algorithm

Figure 4.32 MDL modulation depth

Figure 4.33 Maximum displacement by waveform read address

Figure 4.34 Address displacement during FM synthesis

Figure 4.35 Wave data during clipping processing

Figure 4.36 Number of slot connections

Figure 4.37 Self-feedback modulation

Figure 4.38 Multi-stage feedback

Figure 4.39 Composite feedback

Figure 4.40 Complex modulation

Figure 4.41 FM configuration algorithm pattern 1

Figure 4.42 FM configuration algorithm pattern 2

Figure 4.43 7-slot FM configuration

Figure 4.44 Wave data when TL bit4=1

Figure 4.45 Relationship between OCT and FNS

Figure 4.46 LFO block diagram

Figure 4.47 Digital mixer block diagram

Figure 4.48 Path of direct component and effect component

Figure 4.49 Localization calculation using DSP

Figure 4.50 Digital mixer block diagram

Figure 4.51 SCSP and DAC connection

Figure 4.52 Memory address mapping diagram

Figure 4.53 MIDI-I/F block diagram

Figure 4.54 MIDI OUT section and interrupt generation section

Figure 4.55 Sound interrupt signal connection diagram

Figure 4.56 Interrupt register bit correspondence

Figure 4.57 Correspondence between 3-bit code and register

Figure 4.58 Interrupt level setting register format

Figure 4.59 DMA controller block diagram

Chapter 5 Operation of DSP in SCSP

Figure 5.1 DSP configuration diagram