Table of Contents

Table

• Table 1.1 Sound CPU address 100400H, 100401H
• Table 1.2 Sound CPU Interrupt Vector Table

• Table 2.1 Sound CPU specifications
• Table 2.2 SCSP LSI specifications (1)
• Table 2.3 SCSP LSI specifications (2)

• Table 4.1 Control registers by slot (1)
• Table 4.2 Control registers by slot (2)
• Table 4.3 Control register address map by slot
• Table 4.4 SCSP Common Control Register
• Table 4.5 Sound data stack
• Table 4.6 DSP Control Register
• Table 4.7 DSP microprogram
• Table 4.8 DSP buffer
• Table 4.9 Sound source register allocation
• Table 4.10 KYONB function
• Table 4.11 SBCTL functions
• Table 4.12 SSCTL breakdown
• Table 4.13 Sound data types
• Table 4.14 Loop types
• Table 4.15 Modulation by register setting value
• Table 4.16 Relationship between MDXSL / MDYSL and slots
• Table 4.17 Address maximum displacement by register setting value
• Table 4.18 TL, attenuation and waveform amplitude
• Table 4.19 Actual frequency for cents
• Table 4.20 FNS.OCT parameter table
• Table 4.21 Oscillator frequency
• Table 4.22 AM modulated waveform with LFO
• Table 4.23 PM modulated waveform with LFO
• Table 4.24 Degree of amplitude modulation and frequency modulation
• Table 4.25 Relationship between the number of sources that can be input to IMXL and MIXS
• Table 4.26 Mix register input level
• Table 4.27 D / A converter output level
• Table 4.28 Localization data by DIPAN
• Table 4.29 Sending level to D / A converter
• Table 4.30 Localization data by EFPAN
• Table 4.31 EFSDL and EFPAN register addresses corresponding to each EFREG and EXTS
• Table 4.32 Memory capacity
• Table 4.33 Timer A increment cycle
• Table 4.34 Timer B increment cycle
• Table 4.35 Timer C increment cycle
• Table 4.36 Count cycle for TACTL, TBCTL, TCCTL set values ​​
• Table 4.37 Minimum interrupt time and maximum interrupt time
• Table 4.38 Interrupt register bit sources
• Table 4.39 DMA transfer direction
• Table 4.40 DMA transfer
• Table 4.41 RBL and ring buffer length

Figure

• Figure 1.1 Sound system and peripheral parts
• Figure 1.2 Sound system configuration
• Figure 1.3 Memory map of sound memory register
• Figure 1.4 Sound memory area
• Figure 1.5 Interrupt relationship

• Figure 2.1 SCSP chip block diagram

• Figure 3.1 Access Overview
• Figure 3.2 Memory access priority

• Figure 4.1 SCSP Memory Map
• Figure 4.2 Control registers by slot
• Figure 4.3 SCSP Common Control Register
• Figure 4.4 Sound data stack
• Figure 4.5 DSP Control Register
• Figure 4.6 DSP microprogram map
• Figure 4.7 DSP buffer map
• Figure 4.8 KEY_ON and KEY_OFF sequence
• Figure 4.9 Relationship between block diagram related to noise generation and LFO
• Figure 4.10 Types of loops
• Figure 4.11 Loop waveform
• Figure 4.12 KEY_OFF during attack state transition
• Figure 4.13 KEY_OFF during decay state transition
• Figure 4.14 Change in attenuation
• Figure 4.15 Transition from Attack State to Decay 1 (1)
• Figure 4.16 Transition from Attack State to Decay 1 (2)
• Figure 4.17 Transition from Attack State to Decay 1 (3)
• Figure 4.18 Slot block diagram
• Figure 4.19 Waveform Address Generation Operation Unit
• Figure 4.20 Waveform Address Generation
• Figure 4.21 Address pointer output enlarged view
• Figure 4.22 Frequency address pointer output value
• Figure 4.23 Address pointer output value when FM speech synthesis is executed (1)
• Figure 4.24 Address pointer output value when FM speech synthesis is executed (2)
• Figure 4.25 Normal loop
• Figure 4.26 Reverse loop
• Figure 4.27 Alternative Loop
• Figure 4.28 FM sound source configuration
• Figure 4.29 Averaging Expression
• Figure 4.30 Slot operation and sound stack status
• Figure 4.31 Time difference until the slot is written to the sound stack
• Figure 4.32 Slot averaging operation
• Figure 4.33 Four-slot configuration algorithm
• Figure 4.34 Slot 0 algorithm
• Figure 4.35 Slot 2 algorithm
• Figure 4.36 Slot 2 algorithm (by input slot)
• Figure 4.37 Slot 3 algorithm
• Figure 4.38 MDL modulation depth
• Figure 4.39 Maximum Displacement by Waveform Read Address
• Figure 4.40 Address displacement during FM synthesis
• Figure 4.41 Wave data during clipping process
• Figure 4.42 Number of connected slots
• Figure 4.43 Self-feedback modulation
• Figure 4.44 Multistage feedback
• Figure 4.45 Compound Feedback
• Figure 4.46 Composite modulation
• Figure 4.47 FM composition algorithm pattern 1
• Figure 4.48 FM composition algorithm pattern 2
• Figure 4.49 7-slot FM configuration
• Figure 4.50 Wave data when TL bit4 = 1
• Figure 4.51 Relationship between OCT and FNS
• Figure 4.52 LFO block diagram
• Figure 4.53 Digital mixer block diagram
• Figure 4.54 Path of direct component and effect component
• Figure 4.55 Localization with DSP
• Figure 4.56 Digital Mixer Block Diagram
• Figure 4.57 Connection between SCSP and DAC
• Figure 4.58 Memory address mapping diagram
• Figure 4.59 MIDI-I / F block diagram
• Figure 4.60 MIDI IN section and interrupt generation section
• Figure 4.61 MIDI OUT section and interrupt generation section
• Figure 4.62 Sound Interrupt Signal Connection Diagram
• Figure 4.63 Bit correspondence of interrupt register
• Figure 4.64 Correspondence between 3-bit code and register
• Figure 4.65 Interrupt Level Setting Register Format
• Figure 4.66 DMA Controller Block Diagram

• Figure 5.1 DSP configuration diagram