Correspondence between 3-bit code and register
4SLOT configuration algorithm
7SLOT FM configuration
[English]
ALFOS
ALFOWS
AR
CA
COEF
D1R
D2R
DAC18B
D / A converter output level
Relationship with D / A converter
D / A converter output level
dB (dB)
Timing when an A-Bus interrupt occurs
DDIR
DEXE
DGATE
DIPAN
Localization data by DIPAN
DISDL
DL
DMA controller block diagram
DMA transfer register
DMA transfer
DMA transfer direction
DMA transfer interface
DMEA
DRGA
DSP………………[1][2]
DSP configuration
DSP configuration diagram
DSP output stage adjustment section
DSP control register
RAM in DSP
DSP buffer
DSP buffer map
DSP input stage arithmetic adjustment section
Localization with DSP
DSP block register
DSP microprogram
DSP microprogram map
DTLG
EFPAN
Localization data by EFPAN
EFREG
EFSDL
EG
EGHOLD
EG register
EXTS
FM
FM composition algorithm pattern
FM sound source configuration diagram ……………… [1] [2]
FM sound source system
Address pointer output value when executing FM speech synthesis
Address displacement during FM synthesis ……………… [1] [2]
FM modulation control register
FNS
FNS.OCT parameter table
IMXL
Relationship between the number of sources that can be input to IMXL and MIXS
ISEL
KEY_ON and KEY_OFF sequences
KRS
KYONB
KYONB function
KYONEX
LEA
LFO………………[1][2]
LFOF
LFORE
AM modulation waveform by LFO
PM modulated waveform by LFO
LFO block diagram
LFO register
LPCTL
LPSLNK
LSA
LSB
LSI overview
LSI specifications
MADRS
MC68EC000
MCIEB
MCIPD
MCIRE
MDL………………[1][2]
MDL modulation depth
Relationship between MDXSL / MDYSL and slots
MDXSL
MDXSL / MDYSL formula
MDYSL
MEM4MB
MEMS
MIBUF
MIDI-I / F block diagram
MIDI IN section and interrupt generation section
MIDI OUT section and interrupt generation section
MIDI interface
MIDI standard
MIDI register
MIEMP
MIFULL
MIOVF
MIXS
MIXER register
MOBUF
MOEMP
MOFULL
MPRO
MSB
MSLC
MVOL
OCT
Relationship between OCT and FNS
PLFOS
PLFOWS
PCM8B
PCM sound source
PG
PITCH register
RBL
RBL and ring buffer length
RBP
RESET
RR
SA
SBCTL
SBCTL function
SCIEB
SCILV0
SCILV1
SCILV2
SCIPD
SCIRE
SCSP
SCSP LSI specifications ……………… [1] [2]
SCSP overview
SCSP function
SCSP common control register (Figure)
SCSP common control register (table)
SCSP chip block diagram
Connection between SCSP and DAC
Operation of DSP in SCSP
SCSP memory map
SCSP interface
SCSP register
SDIR
SOUND STACK
SOUS
SSCTL
SSCTL breakdown
STWINH
TACTL
Count cycle for the set value of TACTL.TBCTL.TCCTL
TBCTL
TCCTL
TEMP
TIMA
TIMB
TIMC
TL
TL, attenuation, and waveform amplitude
Wave data when TL bit4 = 1
[A line]
Access summary
Attack state
Transition from attack state to decay 1 ……………… [1] [1]
KEY-OFF during attack state transition ……………… [1] [2]
Address pointer
Enlarged view of address pointer output
Phase adder
Interface (SCSP)
Interface (Sound CPU)
Interface (Main CPU)
Interpolator
Effect data
Envelope generator
Sound data stack
Alternative loop
Sound source register
Sound source part register allocation
Volume register
[ka line]
External input
EFSDL and EFPAN register addresses corresponding to each EFSDL and EXTS
Career
Clipping process
Wave data during clipping
Attenuation change
[Sa line]
Last stage output adjustment section
Defining the top slot
Minimum interrupt time and longest interrupt time
Sound CPU address 100400H, 100401H
Sound CPU interface ……………… [1] [2]
Sound CPU specifications
Relationship with Sound CPU
Sound CPU interrupt vector table table
Sound system and peripherals
Sound system configuration
Sound system positioning
Start sound system
Sound system communication
Sound stack
Sound data type
Sound memory configuration register
Sound memory map
Sound memory area
Sound memory register memory map
Sound interrupt signal wiring diagram
Number of samples
System configuration
Frequency address pointer output value ……………… [1] [2]
Output mixer
Amplitude and frequency modulation levels
Slot
Time difference before the slot is written to the sound stack
Slot status register
Slot connection formula
Number of slots connected
Slot block diagram
Slot block diagram
Slot averaging operation
Slot-specific control register ……………… [1] [2]
Slot-specific control register address map
Self-feedback
Self-feedback modulation
Cent
Actual frequency relative to cents
[Ta line]
Timer A increment cycle
Timer B increment cycle
Timer C increment cycle
Timer register
Direct audio adjustment section
Direct component and effect component routes
Direct data
Multi-stage feedback
Decay 1 state
Decay 2 state
KEY-OFF during decay state transition
Digital mixer block diagram
Digital mixer block diagram
Data
[Na Line]
Relationship between block diagram related to noise generation and LFO
Normal loop
[Wa]
Waveform RAM
Waveform address generation calculator
Waveform address generation / waveform data reading
Waveform address pointer
Waveform data buffer
Maximum displacement by waveform readout address
Oscillator frequency
Panpot
Phase generator
Composite feedback
Composite modulation
Prescaler
Averaging unit
Averaging expression
【MA Line】
Mix register input level
Main CPU interface ……………… [1] [2]
Relationship with main CPU
Communication with the main system
Main interrupt and SCU DMA
Memory access priority
Memory address mapping diagram
Memory controller
Memory capacity
Modulation level
Modulator
[La line]
Linear
Reverse loop
Release status
Loop control register
Loop type
Loop waveform
Maximum address displacement by register setting value
Modulation by register setting value
Register map
Level calculator
Level multiplication section
[Wa]
Interrupt signal
Interrupt control register
Interrupts
Interrupt register bit support
Interrupt register bit cause
Interrupt level setting register format