Japanese
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``Sega Saturn Overview Manual''
■No. 1: [Correction]・Overall
■No. 2: [Addition]・"Chapter 3 Function" ■3.1 CPU Note
■No. 3: [Addition]・"Chapter 3 Function" ■3.2 SCU● Function
``SCU User's Manual''
■No. 1: [Modification]・Chapter 1 Overview・■1.2 SCU mapping
■No. 2: [Modification]・Chapter 1 Overview・■1.3 SCU register map
■No. 3: [Addition]・Chapter 1 Overview・■1.3 SCU register map
■No. 4: [Deleted]・Chapter 1 Overview・■DMA forced stop register
■No. 5: [Deleted]・Chapter 1 Overview・■DMA status register
■No. 6: [Addition]・Chapter 2 Operation explanation・■2.1 DMA transfer・
■No. 7: [Modification]・Chapter 2 Operation explanation・■2.1 DMA transfer
■No. 8: [Modification]・Chapter 2 Operation explanation・■2.1 DMA transfer
■No. 9: [Modification]・Chapter 2 Operation explanation・■2.1 DMA transfer・◆Specific usage example・●Indirect mode
■No.10: [Modification]・Chapter 3 Register details・■3.1 Register list
■No.11: [Addition]・Chapter 3 Register details・■3.1 Register list
■No.12: [Modification]・Chapter 3 Register details・■3.2 DMA control register・●Number of transferred bytes
■No.13: [Addition]・Chapter 3 Register details・■3.2 DMA control register
■No.14: [Addition]・Chapter 3 Register details・■3.2 DMA control register
■No.15: [Addition]・Chapter 3 Register details・■3.2 DMA control register
■No.16: [Deleted]・Chapter 3 Register details
■No.17: [Addition]・Chapter 3 Register details・■3.2 DMA control register
■No.18: [Addition]・Chapter 3 Register details・■3.3 DMA control port
■No.19: [Addition]・Chapter 3 Register details・■3.5 Interrupt control register
■No.20: [Modification]・Chapter 3 Register details・■3.5 Interrupt control register
■No.21: [Deleted]・Chapter 3 Register details・■3.6 A-Bus control register
■No.22: [Addition]・Chapter 3 Register details・■3.6 A-Bus control register
■No.23: [Addition]・Chapter 3 Register details・■3.7 SCU control register
■No.24: [Modification]・Chapter 4 DSP control・■4.2 Command list
"SCSP User's Manual"
■No. 1: [Modification]・Chapter 1 Sound system configuration
■No. 2: [Addition]・Chapter 2 SCSP overview・■2.2 LSI specifications・●Sound CPU specifications
■No. 3: [Modification]・Chapter 4 SCSP register・4.1 Register map・■SCSP control register
■No. 4: [Change]・Chapter 4 SCSP register・4.1 Register map・■SCSP control register
■No. 5: [Deleted]・Chapter 4 SCSP register・4.1 Register map・■SCSP control register
■No. 6: [Change]・Chapter 4 SCSP register・■4.2 Sound source register
■No. 7: [Deleted]・Chapter 4 SCSP register・■4.2 Sound source register
■No. 8: [Addition]・Chapter 4 SCSP register・■4.2 Sound source register
■No. 9: [Deleted]・Chapter 4 SCSP register・■4.2 Sound source register
``SMPC User's Manual''
■No. 1: [Modification]・Chapter 1 Overview・■1.1 System configuration
■No. 2: [Addition]・Chapter 1 Overview・■1.2 SH-2 Interface・◆Parallel I/O register
■No. 3: [Addition]・Chapter 2 SMPC commands・■2.1 Command list
■No. 4: [Addition]・Chapter 2 SMPC command・■2.2 Command issue
■No. 5: [Addition]・Chapter 2 SMPC commands・■2.1 Command list
■No. 6: [Addition]・Chapter 2 SMPC commands・■2.3 Reset system management commands
■No. 7: [Addition]・Chapter 2 SMPC commands・■2.3 Reset system management commands
■No. 8: [Addition]・Chapter 2 SMPC commands・■2.3 Reset system management commands
■No. 9: [Modification]・Chapter 2 SMPC commands・■2.3 Reset system management commands
■No.10: [Addition]・Chapter 2 SMPC commands・■2.3 Reset system management commands
■No.11: [Addition]・Chapter 2 SMPC commands・■2.3 Reset system management commands
■No.12: [Addition]・Chapter 2 SMPC commands・■2.3 Reset system management commands
■No.13: [Addition]・Chapter 2 SMPC commands・■2.3 Reset system management commands
■No.14: [Modification]・Chapter 2 SMPC commands・■2.3 Reset system management commands
■No.15: [Modification]・Chapter 2 SMPC commands・■2.3 Reset system management commands
■No.16: [Modification]・Chapter 2 SMPC commands・■2.4 Non-reset system management commands
■No.17: [Addition]・Chapter 3 Peripheral Control・3.1 SMPC Control Mode・◆Result parameter details
■No.18: [Addition]・Chapter 3 Peripheral Control・3.1 SMPC Control Mode・◆SH-2 Direct Mode
■No.19: [Addition]・Chapter 3 Peripheral Control・■3.2 Saturn Peripheral Standard Format C Control Mode
■No.20: [Addition]・Chapter 3 Peripheral Control・■3.3 Support Peripheral Data Format
■No.21: [Modification]・Chapter 3 Peripheral Control・■3.3・◆Shuttle Mouse
■No.22: [Modification]・Chapter 3 Peripheral Control・■3.3・◆Sega Saturn standard pad
■No.23: [Modification]・Chapter 3 Peripheral Control・■3.3・◆Mission Stick
■No.24: [Modification]・Chapter 3 Peripheral Control・■3.3・◆Sega Saturn Keyboard
■No.25: [Modification]・Chapter 3 Peripheral Control・■3.3・◆Multi Terminal 6
■No.26: [Addition]・Chapter 3 Peripheral Control・■3.3・◆Multi Controller
■No.27: [Addition]・Chapter 3 Peripheral Control・■3.3・◆Twin Stick
■No.28: [Addition]・Chapter 3 Peripheral Control・■3.3・◆Racing Controller
■No.29: [Modification]・Chapter 3 Peripheral Control・■3.4 Peripheral Access Protocol
■No.30: [Delete]・Chapter 3 Peripheral Control・■3.4 Peripheral Access Protocol
"VDP1 User's Manual"
■No. 1: [Modification]・Chapter 5 Table・■5.2 Color lookup table
■No. 2: [Modification]・Chapter 7 Command・■7.8 Polyline drawing command
"VDP2 User's Manual"
■No. 1: [Addition]・Chapter 1 VDP2 functions・■1.2 Address map
■No. 2: [Addition]・Chapter 1 VDP2 functions・■2.1 TV screen mode
■No. 3: [Addition]・Chapter 1 VDP2 functions・■2.1 TV screen mode
■No. 4: [Addition]・Chapter 2 TV screen・■2.5 External signals and scanning status
■No. 5: [Modification]・Chapter 2 TV screen・■2.5 External signals and scanning status
■No. 6: [Addition]・Chapter 2 TV screen・■3.2 VRAM bank division
■No. 7: [Modification]・Chapter 3 RAM・■3.3 How to access VRAM during the display period
■No. 8: [Addition]・Chapter 4 Scroll screen・■3.3 How to access VRAM during the display period
■No. 9: [Addition]・Chapter 8 Window・■8.1 Window area
■No.10: [Addition]・Chapter 9 Sprite Data・■9.1 Sprite Data
■No.11: [Addition]・Chapter 14 Shadow function・■14.1 Shadow processing
■No.12: [New]・VDP2 User's Manual
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"Sega Saturn Overview Manual"
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■No. 1: [Correction] - Overall
Changed description of frequency unit
Mistake
"KC"
Correct
"KHz"
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■No. 2: [Addition]・"Chapter 3 Function" ■3.1 CPU Note
"Table 3.1.1 SH-2 clock details" added
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■No. 3: [Addition]・"Chapter 3 Function" ■3.2 SCU● Function
Clock number details table in “Operating frequency” section
"Table 3.2.1 SCU-DMA clock details" added
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"SCU User's Manual"
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■No. 1: [Modification]・Chapter 1 Overview・■1.2 SCU Mapping
↓p4,p6
Figure 1.3 SCU mapping (cashe_address) and
Figure 1.5 SCU mapping (Cache_through_address) Medium
・Divide "SOUND area" into "SOUND RAM area" and "SCSP register area"
・"VDP1 area/192Kbyte" → 768Kbyte
Mistake
├────────────┤
│SOUND area │Approx. 1Mbyte
│ │
│ │
├────────────┤
├────────────┤
│VDP1 area │192Kbyte
Correct
├────────────┤
│SOUND RAM │Approx. 1Mbyte
│area │
├────────────┤
│SCSP │
│register │
│area │
├────────────┤
├────────────┤
│VDP1 area │768Kbyte
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■No. 2: [Modification]・Chapter 1 Overview・■1.3 SCU register map
↓p7
Figure 1.6 SCU register map
・"DMA forced stop register" → "Unused"
・"DMA status register" → "Unused"
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■No. 3: [Addition]・Chapter 1 Overview・■1.3 SCU register map
↓p7
- Added notes after "Figure 1.6"
------------------------
Note(!)
- Access (read/write) to unused areas is prohibited.
- Be sure to use the cache-through address when accessing the SCU register.
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■No. 4: [Delete]・Chapter 1 Overview・■DMA forced stop register
↓p8
Delete full text
------------------------------------------------ -----------------------------
■No. 5: [Delete]・Chapter 1 Overview・■DMA Status Register
↓p9
Delete full text
------------------------------------------------ -----------------------------
■No. 6: [Addition]・Chapter 2 Operation explanation・■2.1 DMA transfer・
↓p17
-----------------
Figure 2.3 Added (!) Notes on DMA next to the DMA transferable area when activated from DSP
------------------addition------------------
(!) Notes on DMA
●Prohibition of writing to A-Bus by SCU-DMA
SCU-DMA writes to A-Bus cannot be used.
●Prohibition of writing by SCU-DMA from VDP2 area
Writing by SCU-DMA from the VDP2 area cannot be used.
●SCU-DMA cannot be used for WORKRAM-L
Only WORKRAM-HI (SDRAM: 1Mbyte) can be used with SCU-DMA in WORKRRAM.
●Prohibition of access to A-Bub and B-Bus from the CPU during A-Bus←→B-Bus DMA operation
During DMA operation from A-Bus to B-Bus or from B-Bus to A-Bus, access from the CPU to A-Bus or B-Bus is prohibited.
This is because refresh may no longer occur to SDRAM during wait, resulting in a hang-up.
●Waiting for SCU-DMA activation of A-Bus←→B-Bus when writing to A-Bus and B-Bus by CPU
Write processing by the CPU to A-Bus and B-Bus has priority over SCU-DMA activation of A-Bus and B-Bus.
For example, when the CPU is executing continuous write to VDP1 (B-Bus), if you start SCU-DMA from A-Bus to VDP2 (B-Bus),
the continuous write will end. SCU-DMA will not be started until
However, while SCU-DMA is running, CPU access to A-Bus and B-Bus is put on hold.
●The number of channels that can be used simultaneously with DMA is 2.
The number of channels that can be used simultaneously with guaranteed DMA priority is up to 2 channels.
If three channels are used at the same time, the priority order will be ignored. (DSP DMA instructions are also counted as one channel)
●Starting DMA level 2 is prohibited while DMA level 1 is running.
If DMA level 2 is activated while DMA is activated at level 1, malfunction may occur.
As a countermeasure, please do not start DMA level 2 while starting at DMA level 1.
●Prohibit writing at the corresponding level while DMA is running
The contents of the DMA mode, address update, activation factor selection register, and addition value register must
not be rewritten while the DMA is activated at that level.
If you rewrite it, it will hang.
●Prohibitions of SCU-DMA indirect mode
Disables the use of SCU-DMA indirect mode for reading from the CD buffer.
Please use SCU-DMA direct mode, CPU-DMA or software to transfer.
For transfers using the A-BUS space as the source as well as the CD buffer, only "4-byte addition" can be specified for
the source read address addition value, and "no addition" cannot be set.
This restriction does not apply to SCU-DMA direct mode.
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■No. 7: [Modification]・Chapter 2 Operation explanation・■2.1 DMA transfer
↓p20
Figure 2.6 The order in which parameters are set in the "execution address storage buffer" in the indirect mode DMA transfer operation details has been changed.
Incorrect Correct
Read address of ~ Transfer byte count of ~
Write address of ~ → Write address of ~
Number of transferred bytes of ~ Read address of ~
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■No. 8: [Modification]・Chapter 2 Operation explanation・■2.1 DMA transfer
↓p23
◆Specific usage example・●Indirect mode
Swap all numbers of (transfer byte count) and (transfer destination address) in "Figure 2.8 Example of data writing".
Incorrect Correct
┏━━━━━━━━━━┓ ┏━━━━━━━━━━┓
┃ 4000000H ┃ → ┃ 20H ┃
┠──────────┨ ┠──────────┨
┃ 5C00000H ┃ ┃ 5C00000H ┃
┠──────────┨ ┠──────────┨
┃ 20H ┃ → ┃ 4000000H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ 5E00000H ┃ → ┃ 10H ┃
┠──────────┨ ┠──────────┨
┃ 6080000H ┃ ┃ 6080000H ┃
┠──────────┨ ┠──────────┨
┃ 10H ┃ → ┃ 5E00000H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ DA00000H ┃ → ┃ 15H ┃
┠──────────┨ ┠──────────┨
┃ 6081000H ┃ ┃ 6081000H ┃
┠──────────┨ ┠──────────┨
┃ 15H ┃ → ┃ DA00000H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ ┃ ┃ ┃
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■No. 9: [Modification]・Chapter 2 Operation explanation・■2.1 DMA transfer・◆Specific usage example・●Indirect mode
↓p24
Swap all numbers of (transfer byte count) and (transfer destination address) in "Figure 2.9 Work RAM area contents".
Incorrect Correct
┏━━━━━━━━━━┓ ┏━━━━━━━━━━┓
┃ 20H ┃→┃ 4000000H ┃
┠──────────┨ ┠──────────┨
┃ 5C00000H ┃ ┃ 5C00000H ┃
┠──────────┨ ┠──────────┨
┃ 4000000H ┃→┃ 20H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ 10H ┃→┃ 5E00000H ┃
┠──────────┨ ┠──────────┨
┃ 6080000H ┃ ┃ 6080000H ┃
┠──────────┨ ┠──────────┨
┃ 5E00000H ┃→┃ 10H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ 15H ┃→┃ DA00000H ┃
┠──────────┨ ┠──────────┨
┃ 6081000H ┃ ┃ 6081000H ┃
┠──────────┨ ┠──────────┨
┃ DA00000H ┃→┃ 15H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ 30H ┃→┃ 5000000H ┃
┠──────────┨ ┠──────────┨
┃ 6090000H ┃ ┃ 6090000H ┃
┠──────────┨ ┠──────────┨
┃ 5000000H ┃→┃ 30H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ 25H ┃→┃ D100000H ┃
┠──────────┨ ┠──────────┨
┃ 60A0000H ┃ ┃ 60A0000H ┃
┠──────────┨ ┠──────────┨
┃ D100000H ┃→┃ 25H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
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■No.10: [Modification]・Chapter 3 Register details・■3.1 Register list
↓p40
"Table 3.1 Register List"
"DMA forced stop register" and "DMA status register" in "DMA control register" → Delete
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■No.11: [Addition]・Chapter 3 Register details・■3.1 Register list
↓p40
"Caution" after "Table 3.1 Register List"
Add.
----------------addition----------------
(!) Be sure to use a cache-through address when accessing SCU registers.
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■No.12: [Modification]・Chapter 3 Register details・■3.2 DMA control register・●Number of transferred bytes
↓p42
After "Figure 3.3 Number of Level 0 Transfer Bytes" and "Figure 3.4 Number of Level 2-1 Transfer Bytes"
Error
D0Cxx-0(R/W) DMA level ~
Correct
D0Cxx-0(W) DMA level ~
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■No.13: [Addition]・Chapter 3 Register details・■3.2 DMA control register
↓p42
Added a note regarding "●Number of transferred bytes" .
---------------addition---------------
(!) Disable reading of number of transferred bytes in DMA transfer register
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■No.14: [Addition]・Chapter 3 Register details・■3.2 DMA control register
↓p42
Added " ■Operation when the number of DMA transfer bytes is set to '0' "
--------------- Added ---------------
■Operation when the number of DMA transfer bytes is set to '0'
When the number of transfer bytes of SCU-DMA is set to '0', the number of transfers will be the maximum value for each setting.
detail:
Developer's Information STN-39/SCU-DMA Supplement about the number of bytes transferred
--------------------------------------------------------------------------------
■No.15: [Addition]・Chapter 3 Register details・■3.2 DMA control register
↓p45
"Addition value register "＜ Limitations regarding the addition value register＞ "Add.
-----------------
＜Limitations regarding the addition value register＞
(Omitted below)
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■No.16: [Delete]・Chapter 3 Register details
↓ p47-50
"DMA forced stop register", "DMA status register" → Delete
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■No.17: [Addition]・Chapter 3 Register details・■3.2 DMA control register
↓p52
``Added notes regarding ``◆DSP program control port'' .
------------------------------------
(!) When reading the DSP program control port,
Please be aware that the following phenomena may occur.
1.The V flag (overflow flag) will be cleared.
The V flag cannot be checked during DSP execution.
2.DSP end interrupt factor may not occur.
If you monitor (read) the program end interrupt flag during DSP execution, the DSP end interrupt may not occur,
so if your program uses an interrupt to determine the end of DSP, do not read this address.
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■No.18: [Addition]・Chapter 3 Register details・■3.3 DMA control port
↓p52
Added notes regarding "◆DSP Data RAM Data Port" .
------------------------------------
(!) Caution
Notes on data RAM
If you use the pause function (EP) or the one-step execution function (ES) of the
program control port of the DSP during DSP execution, the data in the data RAM inside the DSP is not guaranteed.
Therefore, please strictly adhere to the following matters.
1. DSP pause function (EP) and one-step execution function (ES) are prohibited from use in actual applications.
(These functions are originally for debugging, and they will work if used when debugging the DSP, but the contents
of the data RAM inside the DSP are no longer guaranteed.)
2. To access the DSP data RAM address port and DSP data RAM data port, make sure that the program execution control
flag (EX) of the DSP control port and the D0-Bus DMA execution flag (T0) are both “0”. Please issue it after that.
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■No.19: [Addition]・Chapter 3 Register details・■3.5 Interrupt control register
↓p57
Added a note regarding the "A-Bus interrupt mask bit" .
------------------------------------
(!) Caution
Be sure to mask (set to 1) the A-Bus interrupt mask bit except for controlling special cartridge-connected
devices.
supplement:
"Special cartridge equipment" refers to "XBAND modem" and "NetLink modem".
Applications using these devices should not mask A-Bus external interrupts.
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■No.20: [Modification]・Chapter 3 Register details・■3.5 Interrupt control register
↓p58
Modified the description of ""◆Interrupt status register".
The sentence after Figure 3.22
Mistake
These status registers are ~
Correct
When writing to the interrupt status register, bits that should be set to indicate that an interrupt has
occurred may not be set. Therefore, writing to this register is prohibited.
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■No.21: [Delete]・Chapter 3 Register details・■3.6 A-Bus control register
↓p62~
"The following bits of "◆A-Bus setting register" have been deleted.
p62, CS0 space read-ahead valid bit
p66, CS1 space read-ahead valid bit
p68, CS2 space read-ahead valid bit
p70, spare space read-ahead valid bit
-------------------------------------------------------------------- ---------
■No.22: [Addition]・Chapter 3 Register details・■3.6 A-Bus control register
↓p72
`` Added notes to ``◆A-Bus refresh register''
-----------------------------
(!) Prevents user modification of the A-Bus refresh output enable bit.
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■No.23: [Addition]・Chapter 3 Register details・■3.7 SCU control register
↓p72
" ◆SDRAM selection register"＜ Supplement about initial values＞ Add
-------------------------------
＜Supplement about initial values＞
At power-on reset, the SDRAM selection bit is set to 2M bits x 2 (RSEL=0).
It is necessary to set RSEL=1 again and change it to 4M bits x 2.
This setting change is done within BOOT-ROM, so there is no need for the user to change it.
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■No.24: [Modification]・Chapter 4 DSP control・■4.2 Instruction list
↓p84
Incorrect
● Constant description
Correct
● DSP program description
For constants or assembler descriptions, see the appendix "SCU DSP Arambula Instruction Manual"
Please refer to.
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![]()
"SCSP User's Manual"
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■No. 1: [Correction]・Chapter 1 Sound system configuration
↓p1~p8
Completely replaced "Chapter 1"
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■No. 2: [Addition]・Chapter 2 SCSP overview・■2.2 LSI specifications・●Sound CPU specifications
↓p11
Added to "■2.2 LSI Specifications"
-----------------------------------
Note 1:
Some commands are prohibited for use on Sega Saturn.
・RESET instruction
・TAS instruction
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■No. 3: [Modification]・Chapter 4 SCSP register・4.1 Register map・■SCSP control register
↓p28
In “Table 4.3 SCSP common control register”
Incorrect
──┬──┬──┬──┬──┬──┬─
− │OF│OE│IO│IF│IE│
──┴──┴──┴──┴──┴──┴─
Correct
──┬──┬──┬──┬──┬──┬─
−−│OF│OE│IO│IF│−−│
──┴──┴──┴──┴──┴──┴─
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■No. 4: [Change]・Chapter 4 SCSP register・4.1 Register map・■SCSP control register
↓p29
Before
"Table 4.4 SCSP Common Control Register"
After
"List 4.2 SCSP common control register"
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■No. 5: [Deleted]・Chapter 4 SCSP register・4.1 Register map・■SCSP control register
↓p29
In "List 4.2 SCSP common control register"
・MIEMP: Input FIFO empty → delete
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■No. 6: [Change]・Chapter 4 SCSP register・■4.2 Sound source register
↓p34
Before
“Table 4.9 Sound source register allocation”
After
"List 4.7 Sound source register allocation data"
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■No. 7: [Deleted]・Chapter 4 SCSP register・■4.2 Sound source register
↓p29
In "■Loop control register" description of "SBCTL" bit
Incorrect
Specifies the bit reversal operation of the sound input data.
Correct
Specifies a bit inversion operation excluding the sign bit of the sound input data.
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■No. 8: [Addition]・Chapter 4 SCSP register・■4.2 Sound source register
↓p89
Added a note to "■Sound memory configuration register" .
-------------------------
Caution (!) Be sure to set "1" in this system.
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■No. 9: [Deleted]・Chapter 4 SCSP register・■4.2 Sound source register
↓p29
In "■MIDI register"
Deleted the entire description of "MIEMP(R);Midi Input EMPty".
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![]()
"SMPC User's Manual"
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■No. 1: [Modification]・Chapter 1 Overview・■1.1 System configuration
↓p4
“●input peripheral”
Incorrect
■PAD
Correct
-----------------------------------
●Input peripherals
◆Sega Saturn standard pad
Digital standard pads for Sega Saturn include top, bottom, left, right, A, B, C, X, Y, Z, L,
Equipped with R and start buttons.
◆Multi controller
The multi-controller is equipped with analog keys and analog LR buttons while maintaining compatibility with
the Sega Saturn standard pad.
Reference: STN-43 “Multi-controller User’s Manual Ver1.00”
◆Mission stick
Reference: STN-34 “Analog Mission Stick Manual”
◆Racing controller
Reference: STN-38 “Racing Controller Manual”
◆Shuttle mouse
Reference: STN-44 “Supplementary explanation of shuttle mouse”
◆Sega Saturn keyboard
Reference: STN-45 “Supplementary explanation of Saturn keyboard”
◆Virtual Gun
Reference: STN-41 “Virtual Gun User’s Manual Ver1.00”
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■No. 2: [Addition]・Chapter 1 Overview・■1.2 SH-2 Interface・◆Parallel I/O register
↓p8
Added notes under "Table 1.4 IOSEL Functions"
---------------------------
(!) Use of SH-2 direct mode is prohibited.
(Excluding peripherals using SH-2 direct mode)
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■No. 3: [Addition]・Chapter 2 SMPC commands・■2.1 Command list
↓p12
Clarified commands that are prohibited from being used by users in "Table 2.1 Reset System Management Commands" . Added under “Table 2.1”.
----------------------
× marks prohibit use by users
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■No. 4: [Addition]・Chapter 2 SMPC Commands・■2.2 Command Issuance
↓p18
Added notes to "●INTBACK command issuance timing after executing SYSRES, CCKHG320, CCKHG352 commands"
----------------------------
(!) When using the clock change command, be sure to use the system library.
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■No. 5: [Addition]・Chapter 2 SMPC commands・■2.1 Command list
↓p20
Commands that are prohibited from being used by users are specified in "Table 2.5 SH-2 Command Issuance Restrictions" . Added under “Table 2.5”.
----------------------
× marks prohibit use by users
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■No. 6: [Addition]・Chapter 2 SMPC commands・■2.3 Reset system management commands
↓p22
"No.1 MSHON" command, added a note to the notes section
--------------------------------------
remarks
User use is prohibited.
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■No. 7: [Addition]・Chapter 2 SMPC commands・■2.3 Reset-related system management commands
↓p24
Added "No.3 SSHOFF" command and notes field
--------------------------------------
remarks
Issuance of this command is prohibited under the following conditions.
When slave SH-2 is accessing external bus (A-Bus, B-Bus, CPU-Bus).
In other words, it cannot be used unless the slave SH-2 is accessing the cache inside the CPU.
If the above management is difficult on the application side, use the system library clock change (SYS_CHGSYSCK).
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■No. 8: [Addition]・Chapter 2 SMPC commands・■2.3 Reset system management commands
↓p25
Added "No.4 SNDON" command and notes section
--------------------------------------
remarks
See "Sound OFF" command.
-----------------------------------------------------------------------------
■No. 9: [Modification]・Chapter 2 SMPC commands・■2.3 Reset system management commands
↓p26
"No.5 SNDOFF" command, corrected the full text in the notes column
------------------------
remarks
When stopping the sound CPU, be sure to strictly observe the following restrictions.
＜＜Limitations on stopping and starting sound blocks＞＞
When the sound block is stopped, there must not be a non-access period of 0.5 seconds or more from the main
system (SH2 side) to the sound RAM.
If you want to stop the sound block, load the sound driver, etc.
Please stop it only for the minimum period necessary and restart it immediately.
If you do not need to use the sound CPU (MC68EC000), use a dummy program.
It is necessary to take measures such as executing (just an infinite loop).
If these restrictions are not observed, the operation of the sound RAM and sound block cannot be guaranteed.
-----------------------------------------------------------------------------
■No.10: [Addition]・Chapter 2 SMPC commands・■2.3 Reset system management commands
↓p27
"No.6 CDON" command, caution added to the notes column
------------------------
remarks
User use is prohibited.
-----------------------------------------------------------------------------
■No.11: [Addition]・Chapter 2 SMPC commands・■2.3 Reset system management commands
↓p28
"No.7 CDOFF" command, added a note to the notes section
------------------------
remarks
:
:
User use is prohibited.
-----------------------------------------------------------------------------
■No.12: [Addition]・Chapter 2 SMPC commands・■2.3 Reset system management commands
↓p29
"No.8 SYSRES" command, added a note to the notes section
--------------------------------------
remarks
:
:
User use is prohibited.
-----------------------------------------------------------------------------
■No.13: [Addition]・Chapter 2 SMPC commands・■2.3 Reset system management commands
↓p30
"No.9 CKCHG352" command, added a note to the notes section
------------------------
remarks
:
:
User use is prohibited.
If used, change the clock in the system library (SYS_CHGSYSCK)
Please use
-----------------------------------------------------------------------------
■No.14: [Modification]・Chapter 2 SMPC commands・■2.3 Reset system management commands
↓p33
"No.12 RESENAB" Corrected the command and function contents column
Incorrect
Functional details
This command enables ~.
In addition, the default when the power is turned on ~
Correct
------------------------
Functional details
This command enables ~.
The default value when booting with BOOR ROM is enabled.
-----------------------------------------------------------------------------
■No.15: [Modification]・Chapter 2 SMPC commands・■2.3 Reset system management commands
↓p34
"No.13 RESDISA" Corrected the command and function content column
Incorrect
Functional details
This command enables ~.
In addition, the default when the power is turned on ~
Correct
------------------------
Functional details
This command enables ~.
The default value when booting with BOOR ROM is enabled.
-----------------------------------------------------------------------------
■No.16: [Modification]・Chapter 2 SMPC commands・■2.4 Non-reset system management commands
↓p40
"No.1 INTBACK" command,
Corrected the “●OREG9” area code table,
"5H", "5H", "5H", "5H" changed to "SEGA RESERVED"
-----------------------------------------------------------------------------
■No.17: [Added]・Chapter 3 Peripheral Control・3.1 SMPC Control Mode・◆Details of result parameters
↓p68
"Table 3.7 Multi-tap ID and number of connectors" Added "SEGA reservation"
-------------------------------------------------------------------------------
■No.18: [Addition]・Chapter 3 Peripheral Control・3.1 SMPC Control Mode・◆SH-2 Direct Mode
↓p68
Added notes under "●Features"
-----------------------
(!) If none of the above features apply,
Do not use "SH-2 Direct Mode".
Currently (April 1997), the only peripheral that requires the use of SH-2 Direct Mode is the Virtua Gun.
-----------------------------------------------------------------------------
■No.19: [Addition]・Chapter 3 Peripheral Control・■3.2 Saturn Peripheral Standard Format C Control Mode
↓p68
Added to the bottom of "●Saturn standard format types and data formats"
-----------------------------------
●Future expansion of the standard format
At present, we have the following four formats available, but we plan to add more formats in the future as the need arises.
・Saturn Turn digital device
・Saturn analog device
・Pointing device
・Keyboard device
●Notes on using standard formats
In order to comply with the standard format, if the data size is larger than the standard format, delete excess data before
use. In addition, when the data size is smaller than the standard format, this can be achieved by supplementing the missing
data with other data. Also, as an example of how to handle this on the peripheral side, there are analog XY controls such as
analog joysticks, but if there is no equivalent digital input, using the fact that the analog XY data exceeds a certain value,
There is a possibility that the peripheral side may adopt a method of turning the U, D, L, and R bits ON/OFF.
-----------------------------------------------------------------------------
■No.20: [Addition]・Chapter 3 Peripheral Control・■3.3 Supported Peripheral Data Format
↓p81
Add list
-----------------
・Mega Drive 3 Button Pad
・Mega Drive 6 Button Pad
・Shuttle Mouse
・Sega Tap
・Sega Saturn Standard Pad
・Mission Stick
・Sega Saturn Keyboard
・Multi Terminal 6
・Multi-controller
・Twin stick
・Racing controller
----------------------------------------- ------------------------------------
■No.21: [Modification]・Chapter 3 Peripheral Control・■3.3・◆Shuttle Mouse
↓p81
Incorrect
■Saturn Mouse (tentative name)
Correct
◆Shuttle mouse
-----------------------------------------------------------------------------
■No.22: [Modification]・Chapter 3 Peripheral Control・■3.3・◆Sega Saturn standard pad
↓p82
Incorrect
■Saturn standard PAD (tentative name)
Correct
◆Sega Saturn standard pad
-----------------------------------------------------------------------------
■No.23: [Modification]・Chapter 3 Peripheral Control・■3.3・◆Mission Stick
↓p83
Incorrect
■Saturn analog joystick (tentative name)
Correct
◆Mission Stick
-----------------------------------------------------------------------------
■No.24: [Modification]・Chapter 3 Peripheral Control・■3.3・◆Sega Saturn Keyboard
↓p83
Incorrect
■Saturn Keyboard (tentative name)
Correct
◆Sega Saturn keyboard
-----------------------------------------------------------------------------
■No.25: [Modification]・Chapter 3 Peripheral Control・■3.3・◆Multi Terminal 6
↓p85
Incorrect
■Saturn 6P Multitap (tentative name)
Correct
◆Multi terminal 6
-----------------------------------------------------------------------------
■No.26: [Addition]・Chapter 3 Peripheral Control・■3.3・◆Multi-controller
↓p85?
◆Added multi-controller
----------------------------------------------------------------------------
■No.27: [Added]・Chapter 3 Peripheral Control・■3.3・◆Twin Stick
↓p85?
◆Added twin sticks
----------------------------------------------------------------------------
■No.28: [Addition]・Chapter 3 Peripheral Control・■3.3・◆Racing Controller
↓p85?
◆Added racing controller
----------------------------------------------------------------------------
■No.29: [Modification]・Chapter 3 Peripheral Control・■3.4 Peripheral Access Protocol
↓p86
■3.4 Peripheral Access Protocol
Incorrect
This section shows the peripheral access protocol and data format in SH-2 direct mode.
Correct
This section shows the peripheral access protocol in SH-2 direct mode.
-----------------------------------------------------------------------------
■No.30: [Delete]・Chapter 3 Peripheral Control・■3.4 Peripheral Access Protocol
↓p87
Delete the following items and explanations in ■3.4 Peripheral Access Protocol.
■About the peripheral interface protocol
■Procedure for accessing a peripheral with a Mega Drive peripheral ID other than 5H in SH-2 direct mode
■Procedure for accessing a peripheral with a Mega Drive peripheral ID of 5H in SH-2 direct mode Below
All items after p90
-------------------------------------------------------------------------------
![]()
"VDP1 User's Manual"
-----------------------------------------------------------------------------
■No. 1: [Modification]・Chapter 5 Table・■5.2 Color lookup table
↓p62
In the description of "■5.2 Color lookup table"
Incorrect
~, RGB codes are all valid. The RGB code is MSB=0. The color bank code is ~
Correct
~, RGB codes are all valid. The RGB code is MSB=1. The color bank code is ~
-----------------------------------------------------------------------------
■No. 2: [Modification]・Chapter 7 Command・■7.8 Polyline drawing command
↓p128
■7.8 Polyline drawing command
Incorrect
When the end bit is 0B and the command selection bit is 0100B, it is a polyline drawing command.
Correct
When the end bit is 0B and the command selection bit is 0101B, it is a polyline drawing command.
-----------------------------------------------------------------------------
![]()
"VDP2 User's Manual"
-----------------------------------------------------------------------------
■No. 1: [Addition]・VDP2 User's Manual・Chapter 1 VDP2 Functions・■1.2 Address Map
↓p3
In the description of "■1.2 Address Map"
●VRAM
Incorrect
~ All long word units are possible.
Correct
~ All long word units are possible. However, read access using SCU-DMA must not be performed.
-----------------------------------------------------------------------------
■No. 2: [Addition]・VDP2 User's Manual・Chapter 1 VDP2 functions・■2.1 TV screen mode
↓p12
" Added under "Table 2.1 TV Screen Mode"
----------------------------------
●High resolution mode
Please note the following when setting the TV screen mode to high resolution mode.
- The normal scroll screen (NBG0 to NBG3) is displayed as if the picture when the TV screen mode is normal
mode has been reduced to 1/2 horizontally.
- The rotating scroll plane (RBG0, 1) can be displayed, but the horizontal resolution of the picture will
be the same as when the TV screen mode is normal mode.
- The VRAM cycle pattern register is valid only for T0 to T3, and for T4 to T3.
It is invalid for T7.
- Vertical cell scrolling function cannot be used.
- There will be restrictions on color calculation functions. For details, see "12.1 Color calculation function"
Please refer to.
- Extended color calculation function and blurring calculation function cannot be used.
-----------------------------------------------------------------------------
■No. 3: [Addition]・VDP2 User's Manual・Chapter 1 VDP2 functions・■2.1 TV screen mode
↓p18
Added below table of horizontal resolution bits
---------------------------------
There are restrictions on the combination of TV screen mode settings for VDP1 and VDP2.
Also, the screen display changes depending on the combination of interlace mode settings.
Table 2.2 shows the limitations of TV screen mode settings, and Table 2.3 shows the respective screen
displays depending on the interlace mode settings.
Table 2.2 Restrictions on TV screen mode settings
| VDP2 settings (TVMD:HRESO2..0) |
VDP1 settings (TVMR:TVM2..0) | Setting permission/denial |
Normal mode
(000 or 001) |
Normal 000 | Possible |
|---|
| High resolution 001 | Setting prohibited |
| Rotation 16 010 | Possible |
| Rotation 8 011 | Possible |
| HDTV 100 | Setting prohibited |
High resolution mode
(010 or 011) |
Normal 000 | Possible |
|---|
| High resolution 001 | Possible |
| Rotation 16 010 | Possible |
| Rotation 8 011 | Possible |
| HDTV 100 | Setting prohibited |
Dedicated monitor mode
(100,101,110,111) |
Normal 000 | Possible |
|---|
| High resolution 001 | Setting prohibited |
| Rotation 16 010 | Possible |
| Rotation 8 011 | Possible |
| HDTV 100 | Setting prohibited |
~
Table 2.3 Screen display depending on interlace mode setting
| LSMD value | DIE value | VDP2 display | VDP1 display |
|---|
| 00 | 0 | non-interlaced | non-interlaced |
| 1 | non-interlaced | cannot be displayed correctly |
| 01 | 0 | Single dense interlace | Single dense interlace |
| 1 | Single dense interlace | double dense interlace |
| 11 | 0 | double dense interlace | Single dense interlace |
| 1 | double dense interlace | double dense interlace |
-----------------------------------------------------------------------------
■No. 4: [Addition]・VDP2 User's Manual・Chapter 2 TV screen・■2.5 External signals and scanning status
↓p22
` `V blank flag: Vertical blank flag (VBLANK), bit 3''
Additional sentences
--------------------------
This bit indicates that the TV screen display bit (DISP) in the TV screen mode register is set to 1.
Valid only when V when TV screen display bit (DISP) is 0
The blank flag (VBLANK) is always 1.
-----------------------------------------------------------------------------
■No. 5: [Modification]・VDP2 User's Manual・Chapter 2 TV screen・■2.5 External signals and scanning status
↓p24
In "Table 2.4 V counter register bit contents"
Incorrect
normal │ │ │ │ │ │ │ │ │ │ │
high resolution │V8│V7│V6│V5│V4│V3│V2│V1│V0│Invalid│
... │ │ │ │ │ │ │ │ │ │ │
Correct
normal │ │ │ │ │ │ │ │ │ │ │
high resolution │V9│V8│V7│V6│V5│V4│V3│V2│V1│V0│
... │ │ │ │ │ │ │ │ │ │ │
-----------------------------------------------------------------------------
■No. 6: [Addition]・VDP2 User's Manual・Chapter 2 TV screen・■3.2 VRAM bank division
↓p30
Added "● Pattern name data storage location"
--------------------------------------
●Storage location of pattern name data
The storage location of pattern name data on the scroll surface has the following restrictions, regardless
of whether it is a normal scroll surface or a rotating scroll surface. Table 3.2 below shows the restrictions
on VRAM mode bits and pattern name data storage locations. Note that there are no restrictions on the storage
location of character pattern data or bitmap pattern data.
1. If neither VRAM-A nor VRAM-B is divided into two, storage is possible only
in either VRAM-A or VRAM-B
2. When dividing only VRAM-A into two
a) When storing in VRAM-B, you can store in VRAM-A1
b) When not storing in VRAM-B, store in either VRAM-A0 or A1.
3. When dividing only VRAM-B into two
a) When storing in VRAM-A, you can store in VRAM-B1
b) When not storing in VRAM-A, store in either VRAM-B0 or B1.
4. If both VRAM-A and VRAM-B are divided into two, data can only be stored in
either VRAM-A0 or VRAM-B0, and either VRAM-A1 or VRAM-B1.
Table 3.2 Limitations on pattern name data storage location
VRAM mode bit setting value | Pattern name data storage location |
|---|
| VRAMD | VRBMD | VRAM-A | VRAM-B |
|---|
| VRAM-A0 | VRAM-A1 | VRAM-B0 | VRAM-B1 |
|---|
| 0 | 0 | ○ | × |
| × | ○ |
| 1 | 0 | × | ○ | ○ |
| ○ | ○ | × |
| 0 | 1 | ○ | × | ○ |
| × | ○ | ○ |
| 1 | 1 | ○ | ○ | × | × |
| ○ | × | × | ○ |
| × | ○ | ○ | × |
| × | × | ○ | ○ |
○: Can be stored
×: Cannot be stored
[Note] If there are multiple storage locations, it is not necessary to store in all
------------------------------------------------------------------------------------------
■No. 7: [Modification]・VDP2 User's Manual・Chapter 3 RAM・■3.3 How to access VRAM during the display period
↓p34
In ""●Image data access" ""Table 3.4 Character pattern data read access specification restrictions" was corrected.
Incorrect
<Omitted>
Correct
Table 3.4 Character pattern data read access specification restrictions
item | TV screen mode | character size | Pattern name table data access timing |
|---|
T0 | T1 | T2 | T3 | T4 | T5 | T6 | T7 |
|---|
character putter
table data
Specify access
timing |
normal |
1 cell horizontal x 1 cell vertical
2 cells horizontally x 2 cells vertically |
T0〜T2,
T4～T7 | T0～T3,
T5～T7 | T0～T3,
T6～T7 | T0～T3,
T7 | T0～T3 | T1～T3 | T2, T3 | T3 |
High resolution,
dedicated monitor |
1 cell horizontal x 1 cell vertical |
T0～T2 | T1～T3 | T0,
T2, T3 | T0, T1,
T3 | − | − | − | − |
2 cells horizontally x 2 cells vertically |
T0～T2 | T1～T3 | T2, T3 | T3 | − | − | − | − |
-----------------------------------------------------------------------------
■No. 8: [Addition]・VDP2 User's Manual・Chapter 4 Scroll screen・■3.3 How to access VRAM during display period
↓p34
Explanation added to ""◆Limitations of horizontal flip function bit"
It is shown in ~.
------------------------
◆Limitations of the horizontal inversion function bit The NBG0 and NBG1 inversion function bits are limited to 16
character colors. Valid only when using color or 256 colors. Do not set it to 1 for other character color numbers.
-----------------------------------------------------------------------------
■No. 9: [Addition]・VDP2 User's Manual・Chapter 8 Window・■8.1 Window area
↓p183
"Added explanation under "Table 8.2 Bit contents of window position
register for vertical coordinates"
--------------------------------------
Window position vertical end point coordinate limit
When using a normal window in double-dense interlace mode, set the value of the vertical end point coordinate window
position register (WPEY0:1800C6H,WPEY:1800CEH) to "1FCH~1
Please do not set it to FFH.
Entering these values will disable the window.
-----------------------------------------------------------------------------
■No.10: [Addition]・VDP2 User's Manual・Chapter 9 Sprite Data・■9.1 Sprite Data
↓p204
Next to ""●Sprite color mode"
Added ""●Normal shadow sprite"
--------------------------------------
●Normal shadow sprites
When using palette format sprites, the sprites may not be displayed depending on the sprite character's pixel data
and color bank values (dot color data in the VDP2 hardware manual). This is because the dot data is judged as dot
data for the VDP2 shadow function (normal shadow data). Table 9.2 shows the sprite data that is determined as normal
shadow data depending on the VDP2 sprite type settings.
“14.1 Shadow processing” and “6.4 Shadow processing” in the VDP1 hardware manual CMDCOLR (Color Control Word).
| sprite type | number of colors | pallet code | color bank |
|---|
| Type 0~3,5 |
16
64
128
256 |
1110
xx11 1110
x111 1110
1111 1110 |
xxxx x111 1111 0000
xxxx x111 11xx 0000
xxxx x111 1xxx 0000
xxxx x111 xxxx 0000 |
| Type 4, 6 |
16
64
128
256 |
1110
xx11 1110
x111 1110
1111 1110 |
xxxx xx11 1111 0000
xxxx xx11 11xx 0000
xxxx xx11 1xxx 0000
xxxx xx11 xxxx 0000 |
| type 7 |
16
64
128
256 |
1110
xx11 1110
x111 1110
1111 1110 |
xxxx xxx1 1111 0000
xxxx xxx1 11xx 0000
xxxx xxx1 1xxx 0000
xxxx xxx1 xxxx 0000 |
| Type C~F |
16
64
128
256 |
1110
xx11 1110
x111 1110
1111 1110 |
xxxx xxxx 1111 0000
xxxx xxxx 11xx 0000
xxxx xxxx 1xxx 0000
Not relevant |
| type 8 |
16
64
128
256 |
1110
xx11 1110
x111 1110
1111 1110 |
xxxx xxxx x111 0000
xxxx xxxx x1xx 0000
Not relevant
Not relevant |
| Type 9~B |
16
64
128
256 |
1110
xx11 1110
x111 1110
1111 1110 |
xxxx xxxx xx11 0000
Not relevant
Not relevant
Not relevant |
-----------------------------------------------------------------------------
■No.11: [Addition]・VDP2 User's Manual・Chapter 14 Shadow Function・■14.1 Shadow Processing
↓p258
Added to the description of ""●MSB Shadow"
~Can be specified.
---------------------------------
Please note that the priority number of the transparent shadow sprite uses the value set in sprite
register 0 of the priority number register.
---------------------------------
When using a sprite window, ~
-----------------------------------------------------------------------------
■No.12: [New]・VDP2 User's Manual
↓
Newly added "Chapter 15 How to use VDP2"
----------------------------------------------------------------------------
▲ [Back]
Copyright SEGA ENTERPRISES, LTD., 1997
"Sega Saturn Overview Manual"
-----------------------------------------------------------------------------
■No. 1: [Correction] - Overall
Changed description of frequency unit
Mistake
"KC"
Correct
"KHz"
-----------------------------------------------------------------------------
■No. 2: [Addition]・"Chapter 3 Function" ■3.1 CPU Note
"Table 3.1.1 SH-2 clock details" added
-----------------------------------------------------------------------------
■No. 3: [Addition]・"Chapter 3 Function" ■3.2 SCU● Function
Clock number details table in “Operating frequency” section
"Table 3.2.1 SCU-DMA clock details" added
-----------------------------------------------------------------------------
"SCU User's Manual"
-----------------------------------------------------------------------------
■No. 1: [Modification]・Chapter 1 Overview・■1.2 SCU Mapping
↓p4,p6
Figure 1.3 SCU mapping (cashe_address) and
Figure 1.5 SCU mapping (Cache_through_address) Medium
・Divide "SOUND area" into "SOUND RAM area" and "SCSP register area"
・"VDP1 area/192Kbyte" → 768Kbyte
Mistake
├────────────┤
│SOUND area │Approx. 1Mbyte
│ │
│ │
├────────────┤
├────────────┤
│VDP1 area │192Kbyte
Correct
├────────────┤
│SOUND RAM │Approx. 1Mbyte
│area │
├────────────┤
│SCSP │
│register │
│area │
├────────────┤
├────────────┤
│VDP1 area │768Kbyte
-----------------------------------------------------------------------------
■No. 2: [Modification]・Chapter 1 Overview・■1.3 SCU register map
↓p7
Figure 1.6 SCU register map
・"DMA forced stop register" → "Unused"
・"DMA status register" → "Unused"
-----------------------------------------------------------------------------
■No. 3: [Addition]・Chapter 1 Overview・■1.3 SCU register map
↓p7
- Added notes after "Figure 1.6"
------------------------
Note(!)
- Access (read/write) to unused areas is prohibited.
- Be sure to use the cache-through address when accessing the SCU register.
-----------------------------------------------------------------------------
■No. 4: [Delete]・Chapter 1 Overview・■DMA forced stop register
↓p8
Delete full text
------------------------------------------------ -----------------------------
■No. 5: [Delete]・Chapter 1 Overview・■DMA Status Register
↓p9
Delete full text
------------------------------------------------ -----------------------------
■No. 6: [Addition]・Chapter 2 Operation explanation・■2.1 DMA transfer・
↓p17
-----------------
Figure 2.3 Added (!) Notes on DMA next to the DMA transferable area when activated from DSP
------------------addition------------------
(!) Notes on DMA
●Prohibition of writing to A-Bus by SCU-DMA
SCU-DMA writes to A-Bus cannot be used.
●Prohibition of writing by SCU-DMA from VDP2 area
Writing by SCU-DMA from the VDP2 area cannot be used.
●SCU-DMA cannot be used for WORKRAM-L
Only WORKRAM-HI (SDRAM: 1Mbyte) can be used with SCU-DMA in WORKRRAM.
●Prohibition of access to A-Bub and B-Bus from the CPU during A-Bus←→B-Bus DMA operation
During DMA operation from A-Bus to B-Bus or from B-Bus to A-Bus, access from the CPU to A-Bus or B-Bus is prohibited.
This is because refresh may no longer occur to SDRAM during wait, resulting in a hang-up.
●Waiting for SCU-DMA activation of A-Bus←→B-Bus when writing to A-Bus and B-Bus by CPU
Write processing by the CPU to A-Bus and B-Bus has priority over SCU-DMA activation of A-Bus and B-Bus.
For example, when the CPU is executing continuous write to VDP1 (B-Bus), if you start SCU-DMA from A-Bus to VDP2 (B-Bus),
the continuous write will end. SCU-DMA will not be started until
However, while SCU-DMA is running, CPU access to A-Bus and B-Bus is put on hold.
●The number of channels that can be used simultaneously with DMA is 2.
The number of channels that can be used simultaneously with guaranteed DMA priority is up to 2 channels.
If three channels are used at the same time, the priority order will be ignored. (DSP DMA instructions are also counted as one channel)
●Starting DMA level 2 is prohibited while DMA level 1 is running.
If DMA level 2 is activated while DMA is activated at level 1, malfunction may occur.
As a countermeasure, please do not start DMA level 2 while starting at DMA level 1.
●Prohibit writing at the corresponding level while DMA is running
The contents of the DMA mode, address update, activation factor selection register, and addition value register must
not be rewritten while the DMA is activated at that level.
If you rewrite it, it will hang.
●Prohibitions of SCU-DMA indirect mode
Disables the use of SCU-DMA indirect mode for reading from the CD buffer.
Please use SCU-DMA direct mode, CPU-DMA or software to transfer.
For transfers using the A-BUS space as the source as well as the CD buffer, only "4-byte addition" can be specified for
the source read address addition value, and "no addition" cannot be set.
This restriction does not apply to SCU-DMA direct mode.
-----------------------------------------------------------------------------
■No. 7: [Modification]・Chapter 2 Operation explanation・■2.1 DMA transfer
↓p20
Figure 2.6 The order in which parameters are set in the "execution address storage buffer" in the indirect mode DMA transfer operation details has been changed.
Incorrect Correct
Read address of ~ Transfer byte count of ~
Write address of ~ → Write address of ~
Number of transferred bytes of ~ Read address of ~
-----------------------------------------------------------------------------
■No. 8: [Modification]・Chapter 2 Operation explanation・■2.1 DMA transfer
↓p23
◆Specific usage example・●Indirect mode
Swap all numbers of (transfer byte count) and (transfer destination address) in "Figure 2.8 Example of data writing".
Incorrect Correct
┏━━━━━━━━━━┓ ┏━━━━━━━━━━┓
┃ 4000000H ┃ → ┃ 20H ┃
┠──────────┨ ┠──────────┨
┃ 5C00000H ┃ ┃ 5C00000H ┃
┠──────────┨ ┠──────────┨
┃ 20H ┃ → ┃ 4000000H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ 5E00000H ┃ → ┃ 10H ┃
┠──────────┨ ┠──────────┨
┃ 6080000H ┃ ┃ 6080000H ┃
┠──────────┨ ┠──────────┨
┃ 10H ┃ → ┃ 5E00000H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ DA00000H ┃ → ┃ 15H ┃
┠──────────┨ ┠──────────┨
┃ 6081000H ┃ ┃ 6081000H ┃
┠──────────┨ ┠──────────┨
┃ 15H ┃ → ┃ DA00000H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ ┃ ┃ ┃
-----------------------------------------------------------------------------
■No. 9: [Modification]・Chapter 2 Operation explanation・■2.1 DMA transfer・◆Specific usage example・●Indirect mode
↓p24
Swap all numbers of (transfer byte count) and (transfer destination address) in "Figure 2.9 Work RAM area contents".
Incorrect Correct
┏━━━━━━━━━━┓ ┏━━━━━━━━━━┓
┃ 20H ┃→┃ 4000000H ┃
┠──────────┨ ┠──────────┨
┃ 5C00000H ┃ ┃ 5C00000H ┃
┠──────────┨ ┠──────────┨
┃ 4000000H ┃→┃ 20H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ 10H ┃→┃ 5E00000H ┃
┠──────────┨ ┠──────────┨
┃ 6080000H ┃ ┃ 6080000H ┃
┠──────────┨ ┠──────────┨
┃ 5E00000H ┃→┃ 10H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ 15H ┃→┃ DA00000H ┃
┠──────────┨ ┠──────────┨
┃ 6081000H ┃ ┃ 6081000H ┃
┠──────────┨ ┠──────────┨
┃ DA00000H ┃→┃ 15H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ 30H ┃→┃ 5000000H ┃
┠──────────┨ ┠──────────┨
┃ 6090000H ┃ ┃ 6090000H ┃
┠──────────┨ ┠──────────┨
┃ 5000000H ┃→┃ 30H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ 25H ┃→┃ D100000H ┃
┠──────────┨ ┠──────────┨
┃ 60A0000H ┃ ┃ 60A0000H ┃
┠──────────┨ ┠──────────┨
┃ D100000H ┃→┃ 25H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
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■No.10: [Modification]・Chapter 3 Register details・■3.1 Register list
↓p40
"Table 3.1 Register List"
"DMA forced stop register" and "DMA status register" in "DMA control register" → Delete
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■No.11: [Addition]・Chapter 3 Register details・■3.1 Register list
↓p40
"Caution" after "Table 3.1 Register List"
Add.
----------------addition----------------
(!) Be sure to use a cache-through address when accessing SCU registers.
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■No.12: [Modification]・Chapter 3 Register details・■3.2 DMA control register・●Number of transferred bytes
↓p42
After "Figure 3.3 Number of Level 0 Transfer Bytes" and "Figure 3.4 Number of Level 2-1 Transfer Bytes"
Error
D0Cxx-0(R/W) DMA level ~
Correct
D0Cxx-0(W) DMA level ~
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■No.13: [Addition]・Chapter 3 Register details・■3.2 DMA control register
↓p42
Added a note regarding "●Number of transferred bytes" .
---------------addition---------------
(!) Disable reading of number of transferred bytes in DMA transfer register
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■No.14: [Addition]・Chapter 3 Register details・■3.2 DMA control register
↓p42
Added " ■Operation when the number of DMA transfer bytes is set to '0' "
--------------- Added ---------------
■Operation when the number of DMA transfer bytes is set to '0'
When the number of transfer bytes of SCU-DMA is set to '0', the number of transfers will be the maximum value for each setting.
detail:
Developer's Information STN-39/SCU-DMA Supplement about the number of bytes transferred
--------------------------------------------------------------------------------
■No.15: [Addition]・Chapter 3 Register details・■3.2 DMA control register
↓p45
"Addition value register "＜ Limitations regarding the addition value register＞ "Add.
-----------------
＜Limitations regarding the addition value register＞
(Omitted below)
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■No.16: [Delete]・Chapter 3 Register details
↓ p47-50
"DMA forced stop register", "DMA status register" → Delete
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■No.17: [Addition]・Chapter 3 Register details・■3.2 DMA control register
↓p52
``Added notes regarding ``◆DSP program control port'' .
------------------------------------
(!) When reading the DSP program control port,
Please be aware that the following phenomena may occur.
1.The V flag (overflow flag) will be cleared.
The V flag cannot be checked during DSP execution.
2.DSP end interrupt factor may not occur.
If you monitor (read) the program end interrupt flag during DSP execution, the DSP end interrupt may not occur,
so if your program uses an interrupt to determine the end of DSP, do not read this address.
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■No.18: [Addition]・Chapter 3 Register details・■3.3 DMA control port
↓p52
Added notes regarding "◆DSP Data RAM Data Port" .
------------------------------------
(!) Caution
Notes on data RAM
If you use the pause function (EP) or the one-step execution function (ES) of the
program control port of the DSP during DSP execution, the data in the data RAM inside the DSP is not guaranteed.
Therefore, please strictly adhere to the following matters.
1. DSP pause function (EP) and one-step execution function (ES) are prohibited from use in actual applications.
(These functions are originally for debugging, and they will work if used when debugging the DSP, but the contents
of the data RAM inside the DSP are no longer guaranteed.)
2. To access the DSP data RAM address port and DSP data RAM data port, make sure that the program execution control
flag (EX) of the DSP control port and the D0-Bus DMA execution flag (T0) are both “0”. Please issue it after that.
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■No.19: [Addition]・Chapter 3 Register details・■3.5 Interrupt control register
↓p57
Added a note regarding the "A-Bus interrupt mask bit" .
------------------------------------
(!) Caution
Be sure to mask (set to 1) the A-Bus interrupt mask bit except for controlling special cartridge-connected
devices.
supplement:
"Special cartridge equipment" refers to "XBAND modem" and "NetLink modem".
Applications using these devices should not mask A-Bus external interrupts.
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■No.20: [Modification]・Chapter 3 Register details・■3.5 Interrupt control register
↓p58
Modified the description of ""◆Interrupt status register".
The sentence after Figure 3.22
Mistake
These status registers are ~
Correct
When writing to the interrupt status register, bits that should be set to indicate that an interrupt has
occurred may not be set. Therefore, writing to this register is prohibited.
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■No.21: [Delete]・Chapter 3 Register details・■3.6 A-Bus control register
↓p62~
"The following bits of "◆A-Bus setting register" have been deleted.
p62, CS0 space read-ahead valid bit
p66, CS1 space read-ahead valid bit
p68, CS2 space read-ahead valid bit
p70, spare space read-ahead valid bit
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■No.22: [Addition]・Chapter 3 Register details・■3.6 A-Bus control register
↓p72
`` Added notes to ``◆A-Bus refresh register''
-----------------------------
(!) Prevents user modification of the A-Bus refresh output enable bit.
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■No.23: [Addition]・Chapter 3 Register details・■3.7 SCU control register
↓p72
" ◆SDRAM selection register"＜ Supplement about initial values＞ Add
-------------------------------
＜Supplement about initial values＞
At power-on reset, the SDRAM selection bit is set to 2M bits x 2 (RSEL=0).
It is necessary to set RSEL=1 again and change it to 4M bits x 2.
This setting change is done within BOOT-ROM, so there is no need for the user to change it.
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■No.24: [Modification]・Chapter 4 DSP control・■4.2 Instruction list
↓p84
Incorrect
● Constant description
Correct
● DSP program description
For constants or assembler descriptions, see the appendix "SCU DSP Arambula Instruction Manual"
Please refer to.
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