Table of contents

• Table 2.1 Interrupt factors
• Table 2.2 Interrupt generic term

• Table 3.1 Register list
• Table 3.2 Read address addition value
• Table 3.3 Export address addition value
• Table 3.4 Startup factor details
• Table 3.5 RAM page selection
• Table 3.6 Timer 1 occurrence selection
• Table 3.7 Timer operation contents
• Table 3.8 Interrupt status bit contents
• Table 3.9 A-Bus interrupt acknowledge contents
• Table 3.10 CS0 Spatial Burst Cycle Settings
• Table 3.11 CS0 space normal cycle setting values ​​
• Table 3.12 CS0 space burst length setting value
• Table 3.13 CS0 space bus size setting values ​​
• Table 3.14 CS1 spatial burst cycle setting values ​​
• Table 3.15 CS1 space normal cycle setting values ​​
• Table 3.16 CS1 spatial burst length setting value
• Table 3.17 CS1 space bus size setting values ​​
• Table 3.18 CS2 spatial burst cycle setting values ​​
• Table 3.19 CS2 space bus size setting values ​​
• Table 3.20 Spare space burst cycle setting values ​​
• Table 3.21 Reserve space normal cycle settings
• Table 3.22 Reserve space burst length setting values ​​
• Table 3.23 Spare space bus size settings
• Table 3.24 A-Bus refresh wait count

• Table 4.1 Instruction List (1)
• Table 4.2 Instruction List (2)
• Table 4.3 Instruction List (3)
• Table 4.4 Instruction List (4)
• Table 4.5 Description of constants
• Table 4.6 Features of data transfer from D0 bus to DSP
• Table 4.7 Features of data transfer from DSP to D0 bus

Table of Contents

• Figure 1.1 System configuration diagram
• Figure 1.2 Block diagram
• Figure 1.3 SCU mapping (Cashe_address)
• Figure 1.4 Explanation of operation when a cache hit
• Figure 1.5 SCU mapping (Cashe_through_address)
• Figure 1.6 SCU register map
• Figure 1.7 Level 2-0 DMA set register map
• Figure 1.8 DMA forced stop register map
• Figure 1.9 DMA status register map
• Figure 1.10 DSP Program Control Port Map
• Figure 1.11 DSP Program RAM Data Port Map
• Figure 1.12 DSP Data RAM Address Port Map
• Figure 1.13 DSP Data RAM Data Port Map
• Figure 1.14 Timer 0 Compare Register Map
• Figure 1.15 Timer 1 Set Data Register Map
• Figure 1.16 Timer 1 Mode Register Map
• Figure 1.17 Interrupt mask register map
• Figure 1.18 Interrupt Status Register Map
• Figure 1.19 SCU version register map
• Figure 1.20 A-Bus setting register map
• Figure 1.21 A-Bus refresh register map
• Figure 1.22 A-Bus interrupt acknowledge map
• Figure 1.23 SCU SDRAM Select Register Map

• Figure 2.1 Basic DMA transfer operation
• Figure 2.2 DMA transferable area when started from main CPU
• Figure 2.3 DMA transferable area when activated from DSP
• Figure 2.4 Details of direct mode DMA transfer operation
• Figure 2.5 Indirect mode DMA transfer flow
• Figure 2.6 Indirect mode DMA transfer operation details
• Figure 2.7 Differences in DMA operation due to address update bits
• Figure 2.8 Example of data writing
• Figure 2.9 Work RAM area contents
• Figure 2.10 Example of DMA transfer execution by setting the address addition value
• Figure 2.11 Blanking interrupt details
• Figure 2.12 Timer 0 interrupt generation process (example when compare register = 19)
• Figure 2.13 Timer 1 Interrupt Generation Process (Synchronized with Timer 0)
• Figure 2.14 Timer 1 Interrupt Generation Process (Asynchronous with Timer 0)
• Figure 2.15 Load DSP program Step1
• Figure 2.16 DSP Program Loading Step2
• Figure 2.17 Load DSP program Step3
• Figure 2.18 DSP Data Access Step1
• Figure 2.19 DSP Data Access Step2
• Figure 2.20 DSP data access Step3
• Figure 2.21 DSP CPU execution start control
• Figure 2.22 DSP program forced stop control from CPU

• Figure 3.1 Level 2-0 Read Address (Register: D0R, D1R, D2R)
• Figure 3.2 Level 2-0 write address (Register: D0W, D1W, D2W)
• Figure 3.3 Level 0 Transfer Bytes (Register: D0C)
• Figure 3.4 Level 2-1 Transfer Bytes (Register: D1C, D2C)
• Figure 3.5 Level 2-0 address addition value (register: D0AD, D1AD, D2AD)
• Figure 3.6 SCU-processor communication unit
• Figure 3.7 Example of transfer between SCU and processor
• Figure 3.8 Specifying the export address addition value
• Figure 3.9 Level 2-0 DMA enable bits (registers: D0EN, D1EN, D2EN)
• Figure 3.10 Level 2-0 DMA Mode, Address Update, Activation Factor Selection Register (Register: D0MD, D1MD, D2MD)
• Figure 3.11. DMA forced stop register (register: DSTP)
• Figure 3.12 High and Low Level DMA Operation
• Figure 3.13 DMA Status Register (Register: DSTA)
• Figure 3.14 DSP Program Control Port (Register: PPAF)
• Figure 3.15 DSP Program RAM Data Port (Register: PPD)
• Figure 3.16 DSP Data RAM Address Port (Register: PDA)
• Figure 3.17 DSP Data RAM Data Port (Register: PDD)
• Figure 3.18 Timer 0 Compare Register (Register: T0C)
• Figure 3.19 Timer 1 Set Data Register (Register: T1S)
• Figure 3.20 Timer 1 Mode Register (Register: T1MD)
• Figure 3.21 Interrupt mask register (Register: IMS)
• Figure 3.22 Interrupt status register (register: IST)
• Figure 3.23 A-Bus interrupt acknowledge register (register: AIAK)
• Figure 3.24 A-Bus setting register [CS0,1 space] (Register: ASR0)
• Figure 3.25 A-Bus Setting Register [CS2, Spare Space] (Register: ASR1)
• Figure 3.26 Effect of prefetch processing
• Figure 3.27 Timing when setting precharge insertion bit after write
• Figure 3.28 Timing when setting precharge insertion bit after read
• Figure 3.29 Timing difference due to external wait valid bit setting
• Figure 3.30 A-Bus refresh register (Register: AREF)
• Figure 3.31 SCU SDRAM selection bit (register: RSEL)
• Figure 3.32 SCU version register (register: VER)

• Figure 4.1 DSP internal block diagram
• Figure 4.2 JUMP instruction execution
• Figure 4.3 LOOP program execution
• Figure 4.4 Subroutine program execution
• Figure 4.5 Arithmetic Instruction Format
• Figure 4.6 Load Immediate Instruction Format 1 (Unconditional Transfer)
• Figure 4.7 Load Immediate Instruction Format 2 (Conditional Transfer)
• Figure 4.8 DMA instruction format 1
• Figure 4.9 DMA instruction format 2
• Figure 4.10 JUMP instruction format
• Figure 4.11 LOOP BOTTOM instruction format
• Figure 4.12 END instruction format