[English]
A-Bus
A-Bus control register ……………… [1] [2]
A-Bus setting register (CS0, 1 space)
A-Bus setting register (CS2, and spare space)
A-Bus setting register map
A-Bus refresh wait count
A-Bus refresh register
A-Bus refresh register map
Contents of A-Bus interrupt acknowledge
A-Bus interrupt acknowledge register
A-Bus interrupt acknowledge register map
B-Bus
Forced DSP program stop control from CPU
DSP program execution start control from CPU
CS0,1,2, reserved space A-Bus setting register
CS0 space normal cycle setting value
CS0 space bus size setting value
CS0 space burst cycle setting value
CS0 space burst length setting
CS1 space normal cycle setting value
CS1 space bus size setting
CS1 space burst cycle setting value
CS1 space burst length setting
CS2 space bus size setting value
CS2 space burst cycle setting value
Features of data transfer from D0 bus to DSP
DMA-Illegal interrupt
DMA forced stop register
DMA forced stop register map
DMA enable register
DMA end interrupt
DMA status register ……………… [1] [2]
DMA status register map
DMA control register
DMA transfer basic operation
Execute DMA instruction
DMA instruction format 1
DMA instruction format 2
DMA mode
DMA mode, address update, activation factor selection register
DSP
Features of data transfer from DSP to D0 bus
DMA transferable area when started from DSP
DSP end interrupt
DSP control port
DSP data RAM address port ……………… [1] [2] [3][4]
DSP data RAM address port map
DSP data RAM data port ……………… [1] [2]
DSP data RAM data port map
DSP data access Step1
DSP data access Step2
DSP data access Step3
DSP internal block diagram
DSP program RAM data port ……………… [1] [2]
DSP program RAM data port map
DSP program control port
DSP program control port map
Load DSP program Step1
Load DSP program Step2
Load DSP program Step3
DSP program control port
Execute END instruction
END instruction format
JUMP instruction format
Execute JUMP instruction
Load Immediate instruction format 1 (Unconditional transfer)
Load Immediate Instruction Format 2 (Conditional Transfer)
LOOP BOTTOM instruction format
Run LOOP program
PAD interrupt
RAM page selection
SCSP
SCU
SCU SDRAM selection register map
SCU SDRAM selection bit
SCU overview
SCU control register
SCU version register
SCU version register map
Communication unit between SCU and processor
Specific example of transfer between SCU and processor
SCU mapping (Cashe-address)
SCU mapping (Cashe-through-address)
SCU register map
SMPC
SMPC interrupt
VDP1
VDP2
[A line]
Access, Suspend, Wait, Operation register
Example of DMA transfer execution by address addition value setting
Difference in DMA operation due to address update bits
Operation instruction format
Operand execution method
[ka line]
Timing differences due to external wait valid bit setting
Write address addition value
Specify write address addition value
Indirect mode DMA transfer details
Indirect mode DMA transfer flow
Startup factor details
Explanation of operation when a cache hit
High and low level DMA operation
[Sa line]
Sound-Request interrupt
Effect of prefetching
Subroutine program execution
System configuration diagram
Sprite drawing end interrupt
[Ta line]
Timer 0 compare register
Timer 0 compare register map
Timer 0 interrupt generation process
Timer 1 set data register
Timer 1 set data register map
Timer 1 occurrence selection
Timer 1 mode register
Timer 1 mode register map
Timer 1 interrupt generation process (synchronized with timer 0)
Timer 1 interrupt generation process (asynchronous with timer 0)
Timer operation
Timer register
Direct mode DMA transfer operation details
Constant description
Data
Data writing example (indirect mode)
Executing special processing
[Wa]
Blanking interrupt details
Block diagram
【MA Line】
Main CPU
DMA transferable area when started from main CPU
Instruction list (1)
Instruction list (2)
Instruction list (3)
Instruction List (4)
Instruction details
[Ya]
Read address addition value
Preliminary space normal cycle setting
Preliminary space bus size setting
Preliminary space burst cycle setting value
Preliminary space burst length setting
[La line]
Timing when the precharge insertion bit is set after writing
Timing when setting the precharge insertion bit after reading
Register list
Level 0 transfer byte count
Level 2-0 DMA enable bit
Level 2-0 DMA set register map
Level 2-0 DMA mode, address update, activation factor selection register
Level 2-0 address addition value
Level 2-0 export address
Level 2-0 read address
Level 2-1 bytes transferred
[Wa]
Work RAM area contents
Interrupt address addition value
Interrupt status bit contents
Interrupt status register
Interrupt status register map
Interrupt control register
Interrupt mask register
Interrupt mask register map
Interrupt factor
Interrupt factor generic
[Instruction]
NOP (ALU control)
AND
OR
XOR
ADD
SUB
AD2
SR
RR
SL
RL
RL8
NOP (X-Bus control)
MOV [s],X
MOV MUL,P
MOV [s],P
NOP (Y-Bus control)
MOV [s],Y
CLR A
MOV ALU,A
MOV [s],A
NOP (D1-Bus control)
MV SImm,[d]
MV [s],[d]
MVI Imm,[d]
MVI Imm,[d],Z
MVI Imm,[d],NZ
MVI Imm,[d],S
MVI Imm,[d],NS
MVI Imm,[d],C
MVI Imm,[d],NC
MVI Imm,[d],T0
MVI Imm,[d],NT0
MVI Imm,[d],ZS
MVI Imm,[d],NZS
DMA D0,[RAM],SImm
DMA [RAM],D0,SImm
DMA D0,[RAM],[s]
DMA [RAM],D0,[s]
DMAH D0,[RAM],SImm
DMAH [RAM],D0,SImm
DMAH D0,[RAM],[s]
DMAH [RAM],D0,[s]
JMP Imm
JMP Z,Imm
JMP NZ,Imm
JMP S,Imm
JMP NS,Imm
JMP C,Imm
JMP NC,mm
JMP T0,Imm
JMP NT0,Imm
JMP ZS,Imm
JMP NZS,Imm
BTM
LPS
END
ENDI